Semiconductor Interconnect Liner Design for Resistance Reduction
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Solution Overview
Problem
The complexity of semiconductor device manufacturing leads to issues such as undesirable voids in conductive elements, necessitating an improvement in the manufacturing process to enhance integration and performance.
Innovation Solution
A semiconductor device with an interconnect structure and method that includes a conductive pattern over a semiconductor substrate, an interconnect liner between the interconnect structure and the conductive pattern, and a semiconductor die bonded to the substrate, where the interconnect liner's maximum distance between outer sidewall surfaces is greater than the conductive pattern's width, increasing the contact area and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the interconnect structure width is increased to reduce resistance, then electrical conductivity is improved, but the manufacturing complexity increases due to tighter integration requirements
Solution Approach 1:
The interconnect liner extends beyond the conductive pattern boundaries in the lateral dimension, creating a protruding portion that increases contact area without requiring the interconnect structure itself to be wider. This dimensional extension resolves the contradiction by achieving better electrical conductivity through increased contact area while maintaining the original interconnect width for manufacturing compatibility.
Solution Approach 2:
The interconnect liner acts as an intermediary element between the conductive pattern and the interconnect structure. By extending the liner's contact area with the conductive pattern while keeping the interconnect structure width controlled, it mediates between the need for low resistance and the need for manageable manufacturing complexity.
2Reliability
If the contact area between interconnect structure and conductive pattern is increased to reduce resistance, then electrical performance is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The interconnect liner is formed to extend beyond the conductive pattern boundaries before the interconnect structure is deposited. This preliminary action ensures that when the interconnect structure is subsequently formed, it automatically benefits from the pre-established larger contact area, reducing the precision requirements for subsequent alignment steps.
Solution Approach 2:
The solution addresses the precision issue by extending the contact area in the lateral dimension through the protruding interconnect liner, rather than trying to increase contact area through tighter vertical tolerances or more complex multi-layer structures that would demand higher precision.
3Reliability
If the interconnect liner extends beyond the conductive pattern boundaries, then the contact area is increased and resistance is reduced, but the device structure complexity increases
Solution Approach 1:
The interconnect liner exhibits local quality variation by having different extents in different regions: it extends beyond the conductive pattern boundaries at the contact areas to maximize contact, while remaining contained within boundaries in other regions. This localized extension achieves reduced resistance without requiring the entire structure to be more complex.
Solution Approach 2:
The interconnect liner performs partial extension beyond the conductive pattern boundaries - extending sufficiently to achieve the desired contact area and resistance reduction, but not excessively to create unnecessary structural complexity. This balanced partial action optimizes the trade-off between resistance and structure complexity.
Data Source
AI summary
A semiconductor device includes a conductive pattern disposed over a semiconductor substrate, and an interconnect structure disposed over the conductive pattern. The semiconductor device also includes an interconnect liner formed between the interconnect structure and the conductive pattern and surrounding the interconnect structure. The inner sidewall surfaces of the interconnect liner are in direct contact with the interconnect structure, and a maximum distance between outer sidewall surfaces of the interconnect liner is greater than a width of the conductive pattern. The semiconductor device further includes a semiconductor die bonded to the semiconductor substrate. The semiconductor die includes a conductive pad facing the interconnect structure, wherein the conductive pad is electrically connected to the conductive pattern.