Interconnect Conductive Lines With Local Via-Width Preservation
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Solution Overview
Problem
As semiconductor-based integrated circuits shrink to smaller dimensions, traditional lithography and etch processes face challenges in forming multilayer conductive structures, leading to high electrical leakage due to line-line shorting caused by incomplete metal etching, metal residue, and oxidation of hardmask lines, particularly at deeper levels.
Innovation Solution
A method involving the formation of local hardmask pillars at intended via locations, followed by reducing the width of hardmask lines except at these locations, ensures that conductive lines are narrower except where vias connect to the next level, thereby increasing the distance between adjacent lines and reducing shorting risks while maintaining suitable resistance values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the width of hardmask lines is reduced to increase distance between conductive lines, then line-line shorting is reduced, but via formation becomes difficult at reduced locations
Solution Approach 1:
The patent applies local quality by creating local hardmask pillars at via locations that maintain original line width, while the rest of the hardmask lines are narrowed. This allows via formation to proceed normally at pillar locations while achieving reduced line width and improved electrical isolation in the regions between lines.
Solution Approach 2:
The hardmask line structure is segmented into regular narrowed portions and local pillar portions. The segmentation allows different regions of the same hardmask layer to serve different functions: narrowed regions provide electrical isolation, while pillar regions enable via formation.
2Productivity
If traditional direct metal etching is used, then parallel conductive lines are formed efficiently, but high electrical leakage occurs due to incomplete etching and metal residues
Solution Approach 1:
The patent applies preliminary anti-action by pre-forming local hardmask pillars at via locations before the width reduction step. This preliminary structure prevents the problems of incomplete etching and metal residues by ensuring proper via formation occurs at designated locations, thereby preventing electrical leakage before it can occur.
3Reliability
If hardmask lines are narrowed to prevent oxidation bridging, then line-line shorting is reduced, but via openings cannot be formed
Solution Approach 1:
The patent applies preliminary action by forming local hardmask pillars at via locations before performing the width reduction step. This ensures that when the hardmask lines are narrowed to prevent oxidation bridging, the via locations remain protected by the pillars, allowing subsequent via opening formation to proceed successfully.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces line-line shorting issues and maintains suitable resistance values by ensuring narrower conductive lines except at via locations, enhancing electrical isolation and reducing leakage.
Implementation Method 1
oxidizing the hardmask lines so that in an outer layer of the hardmask lines, the hardmask material is replaced by an oxide layer
Implementation Method 2
removing the oxide layer by etching the oxide layer selectively with respect to the hardmask material of the hardmask lines
Data Source
Figure 1~6
Figure 7~10b
Figure 11~15
AI summary
A method is presented for producing an array of parallel conductive lines (10) in a first level of a multilevel interconnect structure of a semiconductor component. The lines are produced by direct etching, i.e. a conductive layer (2) is produced, a hardmask line pattern (4) is formed on the conductive layer and the line pattern is transferred to the conductive layer by etching the conductive layer relative to the hardmask lines. The hardmask lines are reduced in width prior to the pattern transfer. The width reduction is not done across the full line width of every line : at intended via locations, local hardmask pillars (5) are produced on the hardmask lines prior to the width reduction step, so that the original line width is maintained at the intended via locations. As a result, the width of the conductive lines obtained after the pattern transfer is smaller compared to prior art configurations, except in local areas corresponding to the locations of interconnect vias.