Interconnect Fabric Link Width Adjustment for Dynamic Power Reduction
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Solution Overview
Problem
Current data processing systems face challenges in reducing dynamic power consumption, particularly in graphics processing units (GPUs) with interconnect fabrics, which contribute significantly to power usage.
Innovation Solution
The implementation of dynamic link width reduction techniques based on instantaneous throughput demand, allowing for dynamic bus width allocation and frequency adjustment in interconnect fabrics, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If dynamic link width reduction is implemented based on instantaneous throughput demand, then power consumption is reduced, but link width flexibility and complexity increase
Solution Approach 1:
The patent implements dynamic link width reduction by allowing the interconnect fabric to adjust its operational width based on instantaneous throughput demand. The system transitions from a fixed link width configuration to a dynamic one where link width can be reduced when bandwidth demand is low, thereby reducing power consumption while adapting to varying performance requirements.
Solution Approach 2:
The patent changes the operational parameter of link width from a fixed value to a variable parameter that can be adjusted based on throughput demand. By monitoring instantaneous bandwidth requirements and adjusting link width accordingly, the system achieves power reduction without sacrificing necessary performance capabilities.
2Device complexity
If fixed function computational units are used, then hardware simplicity is maintained, but processing versatility is limited
Solution Approach 1:
The patent enables graphics processors to support multiple processing functions by making portions of the processor programmable. This allows the same hardware to perform both traditional graphics processing and a wider variety of operations including general-purpose computing tasks, thereby achieving versatility without requiring completely separate dedicated hardware for each function.
Solution Approach 2:
The patent applies partial programmability to specific portions of the graphics processor rather than making the entire processor programmable. This selective approach enables versatility in key areas while maintaining hardware simplicity in other areas, achieving a balance between the two competing requirements.
3Speed
If pipelining is implemented to process graphics data in parallel, then processing speed is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic or pulsed operation of the interconnect fabric by reducing link width based on instantaneous throughput demand. Rather than maintaining full bandwidth capability continuously, the system adjusts bandwidth periodically based on actual demand, allowing power reduction during low-demand periods while maintaining high processing speed when needed.
Solution Approach 2:
The patent dynamically adjusts the operational width of the interconnect fabric to match instantaneous throughput demand. This dynamic adaptation allows the system to maintain high processing speeds during high-demand periods while reducing power consumption during low-demand periods, resolving the contradiction between speed and power consumption.
Data Source
AI summary
Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.