Interconnect Fabric Link Width Control for GPU Power Reduction
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Solution Overview
Problem
Current graphics processing units (GPUs) face challenges in managing dynamic power consumption due to fixed interconnect fabric link widths, leading to inefficiencies in power usage and performance.
Innovation Solution
Implementing dynamic link width reduction techniques based on throughput demand, allowing for adjustable bus width and frequency allocation to optimize power usage and performance by allocating reduced bus widths to low-bandwidth modules and full bandwidth to high-bandwidth modules, while enabling more modules to share a bus without increasing contention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If fixed interconnect fabric link widths are used, then device complexity is reduced, but power consumption cannot be dynamically optimized
Solution Approach 1:
The patent implements dynamic link width reduction by allowing the interconnect fabric to change its configuration based on instantaneous throughput demand. The system transitions from fixed link widths to dynamic, adjustable link widths that can be modified at runtime, enabling the fabric to adapt to varying bandwidth requirements and reduce power consumption accordingly.
Solution Approach 2:
The patent changes the physical parameter of link width in the interconnect fabric based on throughput demand. By monitoring instantaneous throughput requirements and adjusting the effective link width accordingly, the system optimizes power consumption while maintaining performance. This involves modifying the number of active lanes or the width of individual links in the fabric.
2Use of energy by moving object
If reduced bus width is allocated to low-bandwidth modules, then power consumption is reduced, but bandwidth availability for high-bandwidth modules may be limited
Solution Approach 1:
The system dynamically allocates bus width based on instantaneous throughput demand rather than providing fixed bandwidth to all modules. When low-bandwidth modules are detected, the system reduces the bus width allocated to them, thereby saving power. When high-bandwidth modules need more bandwidth, the system can reallocate resources dynamically to meet their demands.
Solution Approach 2:
The patent applies different bus widths to different modules based on their specific bandwidth requirements. Instead of uniform treatment, each module receives an appropriately sized bus width matched to its instantaneous throughput demand, optimizing both power consumption and performance for each individual module.
3Device complexity
If more modules share a bus, then device complexity is reduced, but bus contention increases
Solution Approach 1:
The system dynamically adjusts bus width based on instantaneous throughput demand and module requirements. When multiple modules share the bus, the system can dynamically increase the effective bus width during high-demand periods to reduce contention, or maintain narrower widths during low-demand periods to save power. This dynamic adaptation allows more modules to share the bus without proportionally increasing contention.
Data Source
AI summary
Described herein are various embodiments of reducing dynamic power consumption within a processor device. One embodiment provides a technique for dynamic link width adjustment based on throughput demand for client of an interconnect fabric. One embodiment provides for a parallel processor comprising an interconnect fabric including a dynamically configurable bus widths and frequencies.