Interconnect Wire Lithography With Hard Masks for Tighter Spacing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in semiconductor integrated circuits (ICs) is to reduce the spacing between interconnect wires to increase device density while minimizing power consumption and time delay, which is limited by light diffraction and photolithography processes.
Innovation Solution
The method involves using multiple hard mask layers and masking structures to pattern an interconnect dielectric layer, allowing for closer spacing of interconnect wires through precise etching processes, enabling the formation of interconnect wires with smaller distances between them, thereby increasing device density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the spacing between interconnect wires is reduced to increase device density, then the capacitance increases, which increases power consumption and time delay
Solution Approach 1:
The patent applies segmentation by dividing the interconnect wire structure into multiple segments with varying widths. Wider portions are placed where signal strength is sufficient, while narrower portions are used where spacing must be reduced to fit more wires. This segmentation allows the interconnect structure to accommodate higher wire density in constrained areas while maintaining adequate signal integrity in other regions, thereby increasing device density without proportionally increasing power consumption across the entire structure.
Solution Approach 2:
The patent implements local quality by creating non-uniform wire widths along the interconnect paths. Specific segments of wires are made wider or narrower based on local requirements for signal integrity, spacing constraints, and routing density. This localized variation in wire geometry allows optimal balancing between capacitance control and space utilization, enabling increased device density while minimizing power consumption in critical regions.
2Quantity of substance
If the spacing between interconnect wires is reduced to increase device density, then the capacitance increases, which increases time delay
Solution Approach 1:
The patent applies segmentation by dividing the interconnect wire structure into multiple segments with varying widths. Wider portions are placed where signal strength is sufficient, while narrower portions are used where spacing must be reduced to fit more wires. This segmentation allows the interconnect structure to accommodate higher wire density in constrained areas while maintaining adequate signal integrity in other regions, thereby increasing device density without proportionally increasing power consumption across the entire structure.
Solution Approach 2:
The patent implements local quality by creating non-uniform wire widths along the interconnect paths. Specific segments of wires are made wider or narrower based on local requirements for signal integrity, spacing constraints, and routing density. This localized variation in wire geometry allows optimal balancing between capacitance control and space utilization, enabling increased device density while minimizing power consumption in critical regions.
3Ease of manufacture
If photolithography is used to pattern interconnect wires, then the process is simple, but the minimum spacing is limited by light diffraction
Solution Approach 1:
The patent applies the dimensionality change principle by transitioning from two-dimensional planar patterning to three-dimensional vertical structuring. Multiple layers of mandrels and spacers are formed in the vertical dimension, allowing the creation of closely spaced interconnect wires that would be impossible to achieve with single-layer photolithography. This vertical stacking enables spacing below the diffraction limit while maintaining compatibility with standard lithographic processes.
Solution Approach 2:
The patent uses intermediary structures (mandrels and spacers) as mediators to achieve fine feature spacing. The mandrels serve as intermediate templates that are later replaced or surrounded by the final interconnect material. These intermediary elements enable the formation of sub-lithographic features through self-aligned spacer deposition, bridging the gap between photolithography capabilities and the required minimum wire spacing.
Data Source
AI summary
In some embodiments, the present disclosure relates to a method that includes depositing multiple hard mask layers over an interconnect dielectric layer. A first patterning layer is deposited over the multiple hard mask layers, and a first masking structure is formed over the first masking structure. The first masking structure has openings formed by a first extreme ultraviolet (EUV) lithography process. Portions of the first patterning layer are removed according to the first masking structure. A second masking structure is formed within the patterned first patterning layer. A third masking structure is formed over a topmost one of the hard mask layers and has openings formed by a second EUV lithography process. Removal processes are performed to pattern the multiple hard mask layers to form openings in the interconnect dielectric layer, and interconnect wires having rounded corners are formed within the openings of the interconnect dielectric layer.