Interconnect Structure with Lowered Second Conductive Layer

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Solution Overview

Problem

As semiconductor devices miniaturize, overlay shifts between conductive layers can lead to misalignment of vias, causing metal ions to migrate through dielectric layers and result in short circuits, reducing the reliability of interconnect structures.

Innovation Solution

The interconnect structure features a first dielectric layer with trenches for conductive layers, a capping layer covering the conductive layers, and a via positioned between them, ensuring a minimum distance greater than a shift threshold to prevent ion migration, with the top surface of the second conductive layer being lower than the dielectric layer to increase the overlay window and enhance reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the overlay window is reduced due to device miniaturization, then the device size is reduced, but the overlay shift increases causing via misalignment

Engineering Contradiction:
Improvedevice sizeVSAvoidoverlay alignment
Core Design Contradiction:
Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent introduces a vertical dimension solution by forming the second conductive layer at a lower elevation (lower than the top surface of the first dielectric layer). This vertical offset creates additional spatial separation between the via and the second conductive layer, effectively increasing the overlay window in the vertical dimension while maintaining horizontal miniaturization.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The first dielectric layer acts as an intermediary barrier between the via and the second conductive layer. By positioning the second conductive layer below the first dielectric layer's top surface, the dielectric material provides physical separation and prevents direct contact, thereby reducing the risk of short circuits even when overlay shifts occur.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the via is positioned closer to the second conductive layer, then the device density is increased, but metal ion migration causes short circuits

Engineering Contradiction:
Improvedevice densityVSAvoidshort circuit prevention
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The first dielectric layer serves as an intermediary barrier between the via and the second conductive layer. The patent specifies that the second conductive layer's top surface is lower than the first dielectric layer's top surface, ensuring the dielectric material remains between the via and the second conductive layer, thus preventing metal ion migration paths.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the second conductive layer from the same vertical plane as the via, positioning it at a lower elevation. This spatial extraction removes the potential short circuit pathway by ensuring the via and second conductive layer do not occupy the same vertical space, eliminating the migration route for metal ions.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If the top surface of the second conductive layer is lowered, then the overlay window is increased, but the vertical space is reduced

Engineering Contradiction:
Improveoverlay windowVSAvoidvertical space
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent utilizes the vertical dimension to resolve the contradiction. By lowering the second conductive layer's top surface below the first dielectric layer's top surface, the solution creates additional horizontal overlay window while the vertical space consumption is managed within the existing dielectric layer structure.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10153233B1Interconnect structure and fabricating method thereof
Publication Date: 2018.12.11 MACRONIX INTERNATIONAL CO LTD
  • US10153233B1 patent drawing
  • US10153233B1 patent drawing
  • US10153233B1 patent drawing

AI summary

An interconnect structure including a first dielectric layer, a first conductive layer, a second conductive layer, a capping layer, and a via is provided. The first dielectric layer has a first trench and a second trench. The first conductive layer is located in the first trench. The second conductive layer is located in the second trench, and a top surface of the second conductive layer is lower than a top surface of the first dielectric layer. The capping layer having a via opening exposing a portion of the first conductive layer covers the first dielectric layer, the first conductive layer, and the second conductive layer. The via located on the first conductive layer and the first dielectric layer located between the first conductive layer and the second conductive layer is filled into the via opening and electrically connected to the first conductive layer.