Multi-Voltage Interconnect Margining for PAM-4 BER Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As data rates in serial interconnects increase, maintaining a bit error rate (BER) of 10^-12 becomes challenging due to cross-talk, inter-symbol interference, and channel loss, especially with the deployment of PAM-4 encoding in PCIe Gen 6 and other high-speed interconnects, leading to correlated burst errors across lanes.
Innovation Solution
Implement mechanisms and logic circuitry to address error bursts on each lane and across lanes, including error correlation evaluation, dynamic adjustment to error rates, and the use of Forward Error Correction (FEC) with Error Correcting Code (ECC) and Cyclic Redundancy Check (CRC) to reduce error correlation and improve channel performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data rate in serial interconnects is increased to improve transmission speed, then productivity increases, but bit error rate deteriorates due to cross-talk, inter-symbol interference, and channel loss
Solution Approach 1:
The patent applies preliminary action by inserting training sequences and calibration data before actual data transmission. These preliminary signals allow the receiver to characterize channel responses, estimate equalization parameters, and adjust timing recovery settings before receiving actual data, thereby preparing the system to handle high-speed transmission challenges and reduce errors that would otherwise occur at increased data rates
Solution Approach 2:
The patent implements feedback mechanisms where the receiver measures signal quality metrics (such as eye diagram parameters, jitter, and error rates) and feeds this information back to the transmitter. The transmitter then adjusts transmission parameters including equalization coefficients, signal amplitude, and timing based on this feedback, creating a closed-loop system that maintains reliability even at higher data rates by continuously adapting to channel conditions
2Productivity
If PAM-4 encoding is deployed to increase data capacity, then productivity improves, but signal integrity deteriorates leading to correlated burst errors across lanes
Solution Approach 1:
The patent applies local quality by implementing lane-specific equalization and calibration where each interconnect lane is independently characterized and adjusted. The system measures and compensates for lane-specific impairments such as differential mode noise, crosstalk, and skew individually, allowing each lane to operate at optimal signal quality rather than using a one-size-fits-all approach, thereby maintaining signal integrity in PAM-4 encoding across multiple lanes
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting transmission parameters including signal voltage levels, equalization filter coefficients, and timing offsets based on measured channel conditions. The system continuously monitors signal quality metrics and modifies these parameters to compensate for PAM-4 specific challenges such as reduced noise margins and increased susceptibility to intersymbol interference, thereby maintaining signal integrity at higher data capacities
3Reliability
If error correction mechanisms are added to reduce bit error rate, then reliability improves, but device complexity increases
Solution Approach 1:
The patent applies partial action by implementing selective error correction where not all data requires full error correction processing. The system uses forward error correction (FEC) codes with configurable correction capabilities that match the actual error rates observed in the channel, applying stronger correction only when needed based on channel conditions, thereby reducing the overall complexity burden while maintaining adequate reliability
Solution Approach 2:
The patent introduces intermediary components such as training sequence generators, channel characterization units, and equalization processors that mediate between the physical transmission medium and the error correction logic. These intermediaries preprocess the signals to mitigate channel impairments before error correction is applied, reducing the burden on the error correction mechanisms and allowing simpler, more efficient error correction algorithms to achieve the desired reliability
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
Systems and apparatuses can include a receiver that includes port to receive a flow control unit (Flit) across a link, the link comprising a plurality of lanes. The receiver can also include error detection circuitry to determine an error in the Flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the Flit by the error detection circuitry, a Flit counter to count a number of Flits received, the Flit counter to increment based on receiving a Flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the Flit counter. The systems and apparatuses can apply processes to perform direct BER measurements at the receiver.