Interconnect Memory Routing for I/O Congestion
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Solution Overview
Problem
Data storage systems face inefficiencies in processing I/O operations due to the need to access memory components across inter-core links, which slows down memory access times and can lead to congestion on processing cores and links, especially when memory address ranges span across multiple dedicated memory components.
Innovation Solution
Implementing a system with multiple processing cores and dedicated memory components, where an interconnect component with memory routing logic determines the appropriate processing core for each memory address range, routing I/O operations directly to the core connected to the corresponding memory component, thereby avoiding inter-core links and using a uniform memory access scheme to allocate memory space in an interleaved manner between components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If memory address ranges span across multiple dedicated memory components and I/O operations route through inter-core links, then memory access coverage is improved, but memory access time increases and congestion occurs
Solution Approach 1:
The patent segments the memory address space into distinct ranges, each mapped to a specific processing core's dedicated memory component. The interconnect component maintains a mapping table that divides memory address ranges among multiple processing cores, allowing I/O operations to be routed to the appropriate core based on the target memory address. This segmentation eliminates the need for operations to traverse inter-core links, reducing memory access time while maintaining comprehensive memory coverage.
Solution Approach 2:
The patent implements local quality by dedicating specific memory components to specific processing cores and routing I/O operations locally when possible. Each processing core has direct access to its dedicated memory component without needing to communicate through inter-core links. The interconnect component determines the appropriate processing core based on the memory address range, enabling local processing that avoids the performance penalty of inter-core communication.
2Adaptability or versatility
If I/O operations are routed through inter-core links to access memory components, then memory access flexibility is improved, but congestion on processing cores and links increases
Solution Approach 1:
The patent segments I/O operations based on their target memory address ranges, routing each operation to the processing core that owns the corresponding dedicated memory component. The interconnect component uses a mapping table to determine the appropriate core for each memory address range, distributing operations across multiple cores rather than concentrating them on a single core. This segmentation reduces congestion on any single core and inter-core links while maintaining flexible memory access.
Solution Approach 2:
The interconnect component acts as an intermediary between external components and processing cores, intelligence to route I/O operations to the appropriate processing core based on memory address ranges. By inserting this intermediary layer, the system achieves flexible memory access routing without the congestion that would result from all operations funneling through a single core or using inter-core links. The interconnect component balances the workload across multiple processing cores.
3Adaptability or versatility
If multiple processing cores share access to memory components, then resource utilization is improved, but memory access time increases due to inter-core link traversal
Solution Approach 1:
The patent segments memory components into dedicated assignments for each processing core, with each core having direct access to its own memory component. The interconnect component maintains a mapping between memory address ranges and the processing cores that own the corresponding memory components. This segmentation ensures that I/O operations accessing a particular memory component are routed directly to the owning core, eliminating inter-core link traversal and maintaining high memory access speed while still utilizing multiple cores for parallel processing.
4Device complexity
If I/O operations are concentrated on a single processing core, then system simplicity is improved, but congestion and performance degradation occur
Solution Approach 1:
The patent segments I/O operations based on their target memory address ranges, distributing them across multiple processing cores. The interconnect component uses a mapping table to determine which processing core should handle each operation based on the memory address range, automatically balancing the workload. This segmentation approach maintains relative system simplicity while dramatically improving I/O processing throughput by utilizing multiple cores in parallel rather than concentrating all operations on a single core.
Data Source
AI summary
A system may include a plurality processing cores for processing I/O operations and at least one interconnect component for communicatively coupling one or more external components to the plurality of processing cores. The at least one interconnect component may be directly physically connected to each of the plurality of processing cores. The interconnect component may route I/O operations to one of the processing cores based on a memory range of the I/O operation. An I/O communication including an I/O operation may be received at the interconnect component. The memory address range of the I/O operation may be determined. A processing core corresponding to the determined memory address range of the I/O operation may be determined, for example, by accessing a data structure that maps address ranges to processing cores. An I/O communication including the I/O operation may be sent from the interconnect component to the determined processing core.