Interconnect Metal Removal With Dielectric Backfill for HV Isolation
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Solution Overview
Problem
The miniaturization of semiconductor devices leads to complex processing challenges in forming interconnects, particularly due to the introduction of conductive float interconnects which cause undesired capacitance and electrostatic couplings, and occupy valuable space in integrated circuitry, especially in high-voltage applications.
Innovation Solution
A process for selectively removing metal from conductive interconnects in semiconductor dies, involving the use of patterned photoresist layers and etch processes to create openings that are then filled with dielectric material, thereby decoupling neighboring interconnects and reducing capacitance and electrostatic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive float interconnects are introduced to maintain separation between high-voltage and ground interconnects, then electrical isolation is improved, but device complexity and fabrication specificity increase
Solution Approach 1:
The patent removes the problematic conductive float interconnects entirely and replaces them with dielectric material. This extraction eliminates the need for complex fabrication processes while maintaining electrical isolation between high-voltage and ground interconnects through the insulating properties of the dielectric filler.
Solution Approach 2:
The invention changes the material parameter from conductive (metal float interconnect) to insulating (dielectric material). This parameter change fundamentally alters the electrical properties while simplifying the fabrication process, as the dielectric material can be deposited using standard processes without requiring high-specificity fabrication steps.
2Reliability
If conductive float interconnects are used to maintain defined separation, then electrical isolation is improved, but area consumption increases
Solution Approach 1:
By extracting the conductive float interconnects and replacing them with dielectric material, the patent eliminates the additional area that would be required for separate isolation structures. The dielectric filler occupies the same space as the removed float interconnects, providing isolation without increasing overall area consumption.
3Area of stationary object
If tight pitched interconnects are implemented to reduce area, then area efficiency is improved, but spurious electrostatic couplings increase
Solution Approach 1:
The patent introduces dielectric material as an intermediary substance between adjacent interconnects. This intermediary layer acts as an electrical insulator that prevents spurious electrostatic couplings while allowing the interconnects to be placed in tight pitch configurations, thus maintaining area efficiency without the harmful coupling effects.
4Reliability
If conductive float interconnects are introduced, then electrical isolation is improved, but undesired capacitance increases
Solution Approach 1:
The patent changes the electrical parameter of the isolation material from conductive to insulating. By using dielectric material instead of conductive float interconnects, the invention eliminates the parasitic capacitance that would be formed by conductive structures, while maintaining electrical isolation through the high resistivity of the dielectric material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies circuit design, reduces the area occupied by high-voltage interconnects, and minimizes undesired capacitance and electrostatic effects, while being compatible with existing process flows and avoiding the need for redesigning metal densities or plug sizes.
Implementation Method 1
subjecting the metallized film to an etch process to remove an amount of metal according to the feature in the pattern
Implementation Method 2
filling with dielectric material the opening formed after the removal of the metal
Data Source
AI summary
Techniques for selectively removing a metal or conductive material during processing of a semiconductor die for high-voltage applications are provided. In some embodiments, the techniques treat a metallized semiconductor die to transfer a feature from a patterned photoresist layer deposited on the metallized semiconductor die. In addition, the patterned metallized semiconductor die can be subjected to an etch process to remove an amount of metal according to the feature in the pattern, resulting in a treated metallized semiconductor die that defines an opening adjacent to at least a pair of neighboring metal interconnects in the die. The treated metallized semiconductor die can be further treated to backfill the opening with a dielectric material, resulting in a metallized semiconductor die having a backfilled dielectric member. Such a metallized semiconductor die can be further processed according to a process of record until metallization, after which additional selective removal of another amount of metal can be implemented. Semiconductor dies having neighboring metal interconnects separated by backfilled dielectric regions also are provided.