Interconnect Structure Metal Layer Stress Reduction

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Solution Overview

Problem

Conventional interconnect structure manufacturing processes result in high stress and increased costs due to blanket deposition of metal layers, which affects the reliability and stability of the interconnects.

Innovation Solution

A method is introduced where a first mask layer is formed on a portion of the dielectric layer to shield parts of the substrate, reducing the amount of deposited metal and thereby reducing stress, while also forming a lower portion of a second interconnect layer concurrently, thus minimizing the need for additional photolithography and etch processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If blanket deposition of metal layers is performed on the entire dielectric layer surface, then complete coverage is achieved, but stress in the metal layers increases and manufacturing costs increase

Engineering Contradiction:
Improveinterconnect reliabilityVSAvoidmetal layer stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

The patent applies local quality by selectively depositing metal layers only in specific regions where interconnects are needed, rather than performing blanket deposition across the entire dielectric layer surface. This is achieved through localized masking techniques that prevent metal deposition in areas where interconnects are not required, thereby reducing overall metal layer stress while maintaining complete coverage in the necessary regions.

Inventive Principle:
Principle #3Local quality

2Manufacturing precision

If conventional Damascene processes are used with multiple photolithography and etch steps, then precise interconnect formation is achieved, but manufacturing complexity and costs increase

Engineering Contradiction:
Improveinterconnect formation precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple conventional manufacturing steps into a simplified process. By combining the formation of lower and upper interconnect layers into a single deposition cycle with strategic masking, the patent eliminates the need for separate photolithography and etch steps that would otherwise be required for each layer, thereby reducing manufacturing complexity while maintaining precision.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent employs preliminary action by pre-forming the lower interconnect layer and its associated masking structure before depositing the upper interconnect layer. This preliminary configuration allows the upper layer to be deposited directly in the desired pattern without requiring additional photolithography and etching, thus simplifying the overall manufacturing process while achieving precise interconnect formation.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the stress in the metal layers, lowers manufacturing costs, and enhances the reliability and stability of the interconnect structure by controlling the metal deposition and eliminating unnecessary process steps.

Implementation Method 1

depositing a metal layer using an electroplating process to fill the opening and to cover the seed layer on the dielectric layer

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

a metal layer is deposited using an electroplating process to fill the opening and to cover the seed layer on the dielectric layer

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS11373949B2Interconnect structure having metal layers enclosing a dielectric
Publication Date: 2022.06.28 SEMICON MFG INT (SHANGHAI) CORP
  • US11373949B2 patent drawing
  • US11373949B2 patent drawing
  • US11373949B2 patent drawing

AI summary

Interconnect structures are provided. An interconnect structure includes a substrate; a first dielectric layer on the substrate and including an opening for a first interconnect layer extending to the substrate; a first metal layer having a first portion in the opening and a second portion in contact with the first portion and on a portion of the first dielectric layer adjacent to the opening; a second dielectric layer on the first dielectric layer and on the first metal layer, the second dielectric layer including a trench for a second interconnect layer, the trench exposing the second portion of the first metal layer; and a second metal layer in the trench, wherein the second portion of the first metal layer forms a lower portion of the second interconnect layer.