Multi-Drop Interconnect Mode Switching for High Data Rate
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Solution Overview
Problem
Current multi-drop bus technologies, such as the I3C Specification-based bus, face limitations in supporting high data rates and long reach communications, particularly in IoT and automotive applications, with standard modes not meeting the requirements for future generation devices like camera imaging and touch sensors.
Innovation Solution
The implementation of a super high data rate (SHDR) mode that enables differential signaling with a low voltage swing, allowing for higher throughput and reliable communication over longer distances, while maintaining compatibility with existing I2C devices through multiplexing and tunneling techniques, which dynamically adapt communication modes and frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If standard I3C communication modes are used, then compatibility with existing devices is maintained, but data rates and communication distance are limited
Solution Approach 1:
The system dynamically switches between standard I3C communication modes and extended SHDR mode based on device capabilities and communication requirements. The host controller can adaptively select the appropriate mode for each communication session, allowing high-speed operation when needed while maintaining compatibility with legacy devices.
Solution Approach 2:
The patent changes key communication parameters including voltage swing amplitude (reducing to low voltage levels for SHDR mode), data rate, and signaling type (single-ended to differential) to enable extended communication modes. These parameter changes allow the system to achieve higher data rates and longer reach while maintaining backward compatibility through selective parameter application.
2Speed
If additional pins are added to support extended communication modes, then high data rate and long reach are achieved, but device complexity and pin count increase
Solution Approach 1:
The existing I3C bus lines are made multi-functional by enabling them to operate in both standard modes and extended SHDR mode. The same physical pins and wiring infrastructure support multiple communication protocols and modes, eliminating the need for additional dedicated pins for high-speed differential signaling.
Solution Approach 2:
The patent merges the functionality of separate communication channels by enabling the existing single-ended I3C lines to simultaneously or alternately carry differential signals. This consolidation allows extended communication capabilities to be achieved without adding separate physical communication paths or increasing pin count.
3Reliability
If single-ended signaling is used, then compatibility with I2C devices is maintained, but communication distance and reliability are limited
Solution Approach 1:
The host controller acts as an intermediary that translates between single-ended I3C signaling and differential SHDR mode signaling. It converts data and clock signals appropriately based on the communication mode, allowing differential signaling benefits to be achieved while maintaining compatibility with single-ended devices through the mediation of the host controller.
Solution Approach 2:
The system employs periodic mode switching between single-ended and differential signaling based on communication requirements. Differential signaling is activated periodically for high-speed or long-distance segments, while single-ended mode is used for compatibility with legacy devices, creating a rhythmic alternation between signaling types.
Data Source
AI summary
In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.