Interconnect Circuitry for Multi-Transaction Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Modern data processing systems face inefficiencies in memory bandwidth utilization due to cache coherency issues and the need for multiple smaller burst transactions, which increase power consumption and reduce memory efficiency.
Innovation Solution
A data processing system that allows a master device to issue multi-transaction requests, enabling multiple transactions to be routed to appropriate slave devices for processing, with each slave device providing independent responses, thereby optimizing resource utilization and bandwidth efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple smaller burst transactions are issued to maintain cache coherency, then cache coherency is maintained, but memory bandwidth utilization decreases and power consumption increases
Solution Approach 1:
The system segments the multi-transaction request into individual transaction requests for each slave device, allowing parallel processing while maintaining coherency. The interconnect circuitry divides the address range into portions and routes them to appropriate slave devices independently.
Solution Approach 2:
The system merges multiple individual transaction responses into a single multi-transaction response returned to the master device. This combines the results from multiple slave devices into one unified response, reducing the number of response handling operations.
2Reliability
If multiple smaller burst transactions are issued to maintain cache coherency, then cache coherency is maintained, but power consumption increases
Solution Approach 1:
The system segments the multi-transaction request into individual transaction requests for each slave device, allowing parallel processing while maintaining coherency. The interconnect circuitry divides the address range into portions and routes them to appropriate slave devices independently.
Solution Approach 2:
The system enables continuous processing of multiple transactions by different slave devices in parallel, eliminating idle time between transactions. This keeps the memory subsystem continuously utilized with larger effective burst sizes.
3Device complexity
If transactions are limited to single cache line size, then cache coherency is simplified, but the number of transactions required increases
Solution Approach 1:
The interconnect circuitry is designed to handle multiple functions: it distributes address portions to appropriate slave devices, tracks responses from multiple slave devices, and reassembles them into a unified multi-transaction response. This single component performs what would otherwise require multiple separate mechanisms.
Solution Approach 2:
The interconnect circuitry acts as an intermediary between the master device and multiple slave devices. It receives the multi-transaction request, coordinates the distribution to slave devices, collects responses, and returns the consolidated result, simplifying the interface for the master device.
4Reliability
If multiple smaller burst transactions are used, then cache coherency is maintained, but re-ordering capabilities of memory controllers are reduced
Solution Approach 1:
The system segments the multi-transaction request into individual transaction requests for each slave device, allowing parallel processing while maintaining coherency. The interconnect circuitry divides the address range into portions and routes them to appropriate slave devices independently.
Solution Approach 2:
The system enables dynamic re-ordering of transactions by different slave devices based on their individual processing capabilities and queue states. Each slave device can independently reorder its assigned transactions while the overall multi-transaction operation maintains coherence.
Data Source
Figure 1A~1B
Figure 2
Figure 3
AI summary
A data processing system having a master device (55) and a plurality of slave devices (60,62,64) uses interconnect circuitry (50) to couple the master device with the plurality of slave devices to enable transactions to be performed by the slave devices upon request from the master device. The master device issues a multi-transaction request identifying multiple transactions to be performed, the multi- transaction request providing a base transaction identifier, a quantity indication indicating a number of transactions to be performed, and address information. Request distribution circuitry within the interconnect circuitry analyses the address information and the quantity indication in order to determine, for each of the multiple transactions, the slave device that is required to perform that transaction.