Interconnect Structure with Nano-Alloy Barrier
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Solution Overview
Problem
The use of high dielectric constant etch-stop layers in semiconductor manufacturing leads to increased effective capacitance, RC delay, stray capacitance, and scattering issues, while also being costly and unreliable due to adhesion concerns and additional processing requirements.
Innovation Solution
The method involves forming interconnect structures without conventional etch-stop layers by oxidizing and removing a portion of the top surface and side walls of the interconnect structure and covering them with a dissimilar material, such as nano-metals like CoP or NiP, which can act as a coupling, adhesion, or barrier layer, to enhance reliability and reduce scattering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high dielectric constant etch-stop layers are used to control cavity profile, then manufacturing precision is improved, but device performance deteriorates due to increased effective capacitance and RC delay
Solution Approach 1:
The patent removes the etch-stop layer from the interconnect structure entirely, extracting the harmful high dielectric constant material that causes increased capacitance and RC delay. The cavity profile control function is achieved through alternative means (etch process optimization and barrier layer design) without requiring the etch-stop layer, thus eliminating the capacitance penalty while maintaining manufacturing precision.
Solution Approach 2:
The patent changes the dielectric constant parameter of the interconnect structure by eliminating the high dielectric constant etch-stop layer (k=7-9) and replacing it with low dielectric constant materials. This parameter change reduces the effective capacitance and RC delay, improving device performance while the cavity profile is controlled through modified etch process parameters instead.
2Manufacturing precision
If etch-stop layers are used to control cavity profile, then manufacturing precision is improved, but reliability deteriorates due to adhesion concerns and delamination
Solution Approach 1:
The patent extracts and removes the etch-stop layer that causes adhesion problems and delamination. The cavity profile control function is transferred to the barrier layer and etch process optimization, eliminating the adhesion reliability issues associated with etch-stop layers while maintaining precise cavity formation.
Solution Approach 2:
The barrier layer is given multiple functions: it serves as both the etch-stop function (controlling cavity profile) and maintains adhesion reliability. By making the barrier layer multi-functional, the patent eliminates the need for separate etch-stop layers that cause adhesion problems, thus improving reliability while maintaining manufacturing precision.
3Manufacturing precision
If etch-stop layers are used to control cavity profile, then manufacturing precision is improved, but manufacturing cost increases due to additional processing time and expense
Solution Approach 1:
The patent removes the etch-stop layer deposition and removal steps from the manufacturing process, extracting the additional processing time and expense. The cavity profile control is achieved through optimized etch process parameters and barrier layer design, eliminating the need for separate etch-stop layer processing steps and reducing manufacturing cost.
4Manufacturing precision
If etch-stop layers are used to control cavity profile, then manufacturing precision is improved, but device performance deteriorates due to increased stray capacitance and scattering
Solution Approach 1:
The patent extracts and removes the high dielectric constant etch-stop layer that generates stray capacitance and scattering. The cavity profile is controlled through alternative means that do not introduce harmful dielectric materials, thus eliminating stray capacitance and scattering effects while maintaining precise cavity formation for optimal signal integrity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in higher quality and more reliable interconnect structures with reduced scattering and processing costs, as it eliminates the need for high dielectric constant etch-stop layers, improving device performance and yield.
Implementation Method 1
the presence of the high dielectric constant etch-stop increases the effective capacitance of the device, causes higher RC delay, and can cause unwelcomed stray capacitance as well as undesirable scattering in optical devices
Implementation Method 2
oxidizing and removing a portion of the top surface and side walls of the interconnect structure
Data Source
AI summary
Methods and apparatus for forming a semiconductor device are provided which may include any number of features. One feature is a method of forming an interconnect structure that results in the interconnect structure having a top surface and portions of the side walls of the interconnect structure covered in a dissimilar material. In some embodiments, the dissimilar material can be a conductive material or a nano-alloy. The interconnect structure can be formed by removing a portion of the interconnect structure, and covering the interconnect structure with the dissimilar material. The interconnect structure can comprise a damascene structure, such as a single or dual damascene structure, or alternatively, can comprise a silicon-through via (TSV) structure.