Interconnect Structures Nucleation Treatment
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Solution Overview
Problem
The semiconductor industry faces challenges in forming interconnect structures with reduced resistance and increased process windows due to the need for seed layers and high resistance metal-containing barrier layers, which limit the efficiency and complexity of scaling down in IC manufacturing.
Innovation Solution
The method involves forming a dual damascene interconnect structure without a seed layer or metal-containing barrier layer, using a nucleation enhancement treatment to enable bottom-up and conformal deposition of conductive fill materials directly on dielectric surfaces, thereby reducing resistance and increasing process windows.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If seed layers and metal-containing barrier layers are used in interconnect structures, then adhesion and protection are improved, but resistance increases and process complexity worsens
Solution Approach 1:
The patent removes the seed layer and metal-containing barrier layer from the interconnect structure, retaining only the dielectric layer and conductive fill material. This extraction eliminates the high resistance and complexity associated with multiple layers while maintaining adhesion through the dielectric layer alone.
Solution Approach 2:
The patent uses a composite structure consisting of a dielectric layer combined with conductive fill material (such as copper or cobalt). This composite approach replaces traditional metal barrier layers with a dielectric-conductive combination that achieves both adhesion and low resistance properties.
2Strength
If seed layers and metal-containing barrier layers are used, then structural integrity is improved, but device complexity and processing steps increase
Solution Approach 1:
The patent extracts and removes the seed layer and metal-containing barrier layer, reducing the interconnect structure to essential components only. This simplification decreases device complexity and reduces the number of processing steps required for fabrication.
Solution Approach 2:
Instead of adding multiple protective layers to achieve structural integrity, the patent inverts the approach by using a minimal structure with the dielectric layer serving multiple functions. The dielectric layer provides both mechanical support and adhesion, eliminating the need for separate barrier and seed layers.
3Reliability
If conventional interconnect structures with multiple layers are used, then adhesion is improved, but RC delay increases due to higher resistance
Solution Approach 1:
The patent removes the high-resistance seed layer and metal-containing barrier layer, eliminating the primary sources of resistance that contribute to RC delay. The resulting structure has lower resistance while maintaining adhesion through the dielectric layer.
Solution Approach 2:
The patent employs a composite of dielectric layer and conductive fill material that achieves low resistance. The conductive fill material (copper or cobalt) provides excellent electrical conductivity, while the dielectric layer maintains adhesion, together reducing RC delay compared to traditional metal barrier structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the resistance of interconnect structures, decreases RC delay, and enhances processing throughput by allowing bottom-up deposition and conformal filling of trenches, making it suitable for advanced technology nodes like 20 nm and smaller.
Implementation Method 1
A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench
Data Source
AI summary
Embodiments described herein relate generally to one or more methods for forming an interconnect structure, such as a dual damascene interconnect structure comprising a conductive line and a conductive via, and structures formed thereby. In some embodiments, an interconnect opening is formed through one or more dielectric layers over a semiconductor substrate. The interconnect opening has a via opening and a trench over the via opening. A conductive via is formed in the via opening. A nucleation enhancement treatment is performed on one or more exposed dielectric surfaces of the trench. A conductive line is formed in the trench on the one or more exposed dielectric surfaces of the trench and on the conductive via.