High-Density Interconnect Package Layout for Compact High Pin Counts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is an ongoing need for more compact packages that can accommodate high density interconnects and/or high pin counts.
Innovation Solution
A package design that includes a substrate with a cavity, where a high-density interconnect integrated device is located over the cavity, and underfill is placed between the integrated devices and the substrate, allowing electrical signals to bypass the substrate and providing a compact form factor with improved electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional substrate routing is used to accommodate high pin counts, then electrical connection is achieved, but package size increases and routing congestion occurs
Solution Approach 1:
The patent introduces an interconnect integrated device that routes electrical signals in a third dimension by placing it above the substrate cavity. This vertical routing approach allows high pin counts to be accommodated without increasing the lateral package footprint, as signals travel through the Z-axis rather than being constrained to two-dimensional substrate routing.
Solution Approach 2:
The interconnect integrated device acts as an intermediary component between the substrate and the integrated devices. It provides a dedicated routing layer that handles high-density interconnects, freeing the substrate from carrying excessive routing traffic and enabling compact package design while maintaining high pin counts.
2Quantity of substance
If substrate routing is used for high density interconnects, then electrical connection is established, but inductance increases and voltage drop worsens
Solution Approach 1:
By moving the interconnect routing to a vertical dimension through the interconnect integrated device, the patent creates shorter electrical paths between integrated devices. This three-dimensional routing reduces the length of current paths, thereby decreasing inductance and voltage drop compared to traditional planar substrate routing.
3Area of stationary object
If compact package design is implemented, then form factor is reduced, but structural integrity may be compromised
Solution Approach 1:
The patent employs a nested structure where the interconnect integrated device is positioned within the substrate cavity vertically. This nesting approach allows multiple functional layers to occupy the same lateral footprint, achieving compact package size while maintaining structural integrity through the hierarchical arrangement of components.
Solution Approach 2:
The underfill material serves as an intermediary that provides mechanical support and structural integrity to the compact package structure. It fills the cavity space and bonds the interconnect integrated device to the substrate, preventing structural weakness despite the reduced package size.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves a compact form factor with high input/output pin counts, reduced routing congestion, lower inductance, and improved voltage drop, while maintaining strong structural integrity through the use of underfill.
Implementation Method 1
an underfill located (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device
Data Source
AI summary
A package comprising a substrate, a first integrated device coupled to the substrate, a second integrated device coupled to the substrate, an interconnect integrated device coupled to the first integrated device and the second integrated device, and an underfill. The substrate includes a cavity. The interconnect integrated device is located over the cavity of the substrate. The underfill is located (i) between the first integrated device and the substrate, (ii) between the second integrated device and the substrate, (iii) between the interconnect integrated device and the first integrated device, and (iv) between the interconnect integrated device and the second integrated device.