Interconnect Pad Array Layout for Efficient 3D Routing
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Solution Overview
Problem
Existing interconnect structures in stacked semiconductor devices face complexity and inefficiency in routing design, leading to suboptimal utilization of conductive lines and vias for electrical connections between semiconductor wafers or dies.
Innovation Solution
An interconnect structure with a simplified and efficient routing design, featuring aligned arrays of first and second pads connected through conductive lines in different layers, utilizing conductive pillars with alternating vias and landing ports to facilitate electrical connections between pads on different semiconductor wafers or dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional interconnect structures are used in stacked semiconductor devices, then electrical connections between semiconductor wafers or dies can be established, but the routing design becomes complex and inefficient with suboptimal utilization of conductive lines and vias
Solution Approach 1:
The interconnect structure is segmented into multiple functional layers including first and second conductive layers, with conductive pillars containing alternating vias and landing ports. This segmentation allows independent optimization of each layer's routing function, simplifying the overall design while improving resource utilization efficiency
Solution Approach 2:
The patent transitions from planar routing to three-dimensional vertical routing by stacking conductive layers and incorporating conductive pillars with alternating vias and landing ports. This dimensional change enables more efficient use of routing resources in the vertical dimension, reducing design complexity while maintaining connection efficiency
Data Source
AI summary
An interconnect structure includes a plurality of first pads, a plurality of second pads, and a plurality of conductive lines. The first pads are arranged to form a first column-and-row array, and the second pads are arranged to form a second column-and-row array. The first column-and-row array, the second column-and-row array and the conductive lines are disposed in a same layer. The first pads in adjacent rows in the first column-and-row array are separated from each other by a first vertical distance from a plan view, the second pads in adjacent rows in the second column-and-row array are separated from each other by a second vertical distance from the plan view. A sum of widths of the conductive lines electrically connecting the first pads and the second pads in the same row is less than the first vertical distance and the second vertical distance from the plan view.