On-Chip Interconnect Control for Parallel Write Port Transmission

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Solution Overview

Problem

In on-chip interconnection networks, data transmission efficiency is reduced due to the need for destination devices to use a unified write port, leading to lower utilization of write ports and increased waiting times during multicasting or broadcasting.

Innovation Solution

A data transmission system where a processor configures transmission control information to source and destination processing elements, allowing the source to determine data packets and the destination to store data without considering the write port of the destination, thus enabling simultaneous data transmission even when destinations have different write port identifiers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If destination devices use a unified write port for data transmission, then data transmission can be performed, but write port utilization decreases and waiting time increases

Engineering Contradiction:
Improvedata transmission efficiencyVSAvoidwaiting time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The patent segments the write port resource allocation by allowing different destination devices to use different write ports (first write port or second write port) based on their respective data transmission needs, rather than forcing all devices to use a single unified write port. This segmentation enables parallel data transmission to multiple destinations simultaneously, reducing waiting time and improving overall transmission efficiency.

Inventive Principle:
Principle #1Segmentation

2Ease of operation

If destination devices are constrained to use write ports with the same identifier, then unified data transmission is enabled, but write port use efficiency decreases

Engineering Contradiction:
Improveunified data transmissionVSAvoidwrite port use efficiency
Core Design Contradiction:
Ease of operationVSProductivity

Solution Approach 1:

The patent implements dynamic write port selection where destination devices can flexibly choose between a first write port and a second write port based on real-time conditions. The system dynamically determines which write port to use for each destination device, allowing the write port assignment to adapt to varying transmission requirements rather than being statically constrained to a single identifier.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the parameter of write port identifier assignment from a fixed unified value to variable values (first write port identifier or second write port identifier). By allowing the write port identifier parameter to vary based on destination device and transmission conditions, the system achieves both ease of operation and high write port use efficiency.

Inventive Principle:
Principle #35Parameter changes

3Device complexity

If the source device specifies a unified write port for all destinations, then data transmission is simplified, but transmission efficiency is reduced

Engineering Contradiction:
Improvedata transmission controlVSAvoidtransmission efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent introduces an intermediary mechanism where the source device does not directly specify a unified write port for all destinations. Instead, the system uses a intermediate layer that routes data to different write ports based on destination device identification, maintaining simplified source device operation while achieving efficient multi-destination transmission through intelligent routing.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentEP4693057A2Data transmission system and method, medium, device, and chip
Publication Date: 2026.02.11 BEIJING HORIZON INFORMATION TECH CO LTD
  • EP4693057A2 patent drawingFigure 1~2
  • EP4693057A2 patent drawingFigure 3~4
  • EP4693057A2 patent drawingFigure 5~6

AI summary

Embodiments of this disclosure disclose a data transmission system and method, a medium, a device, and a chip. An apparatus includes: a processor; and at least two processing elements, which are interconnected to form an interconnection network. The processor is configured to configure first transmission control information to a first processing element that serves as a source device, and configure second transmission control information to a second processing element that serves as a destination device. The first processing element is configured to: when serving as the source device, determine a to-be-transmitted first data packet based on the first transmission control information, and transmit the first data packet to the second processing element through the interconnection network. The second processing element is configured to: when serving as the destination device, store at least a part of data in the first data packet based on the second transmission control information.