IC Interconnect Parasitic Extraction Across Tiled Layout Regions

The patent divides the design layout into multiple tiles and further segments interconnects into interconnect segments. Field solvers are applied to individual tiles and segments rather than the entire design, reducing computational burden and memory consumption while maintaining accuracy through localized high-resolution analysis.

The patent applies field solvers locally to specific tiles and interconnect segments where high precision is needed, rather than uniformly across the entire design. This allows high-accuracy parasitic extraction for critical regions while using more efficient methods for less critical areas.

The patent segments interconnects into smaller interconnect segments that fall within individual tiles. This segmentation enables the use of field solvers for these smaller segments, achieving both the computational efficiency of divided processing and the accuracy of physics-based solutions for omni-directional and curvilinear geometries.

The patent transitions from applying pattern matching in 2D layout space to applying field solvers in 3D electromagnetic space for interconnect segments. This dimensional transformation allows accurate modeling of complex omni-directional and curvilinear interconnect geometries that cannot be captured by 2D pattern matching.

The patent automatically segments interconnects into smaller interconnect segments that fit within individual tiles. This segmentation provides the field solver with appropriately sized panels (through the segment boundaries) without requiring manual intervention, achieving accurate capacitance calculation with manageable computational resources.

The system automatically determines optimal segment boundaries and panel discretization based on the tile structure and interconnect geometry. This self-service approach ensures that the field solver receives input data with appropriate panel sizes for accurate results without requiring external optimization input.