Interconnect Architecture for Path-Diverse Strongly Ordered Messages
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Solution Overview
Problem
Existing processor designs face challenges with single large die fabrication, which increases yield risk and limits scalability, flexibility, and efficiency due to potential defects and the need for redundant designs.
Innovation Solution
Implementing an interconnect architecture that allows multiple physically separate dies to be connected, forming a processor with a monolithic cache domain, enabling high bandwidth and low latency communication, and allowing for flexible design choices such as 1× or 2× clocking modes to optimize performance and power usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single large die is used for processor fabrication, then integration is simplified, but yield risk increases and scalability is limited
Solution Approach 1:
The processor is divided into multiple smaller physically separate dies that can be fabricated independently and then connected through an interconnect architecture. This segmentation reduces yield risk since smaller dies have lower defect probabilities, while maintaining integration through the interconnect system that provides monolithic cache domain functionality.
2Device complexity
If a single large die is used for processor fabrication, then design is simplified, but scalability and flexibility are limited
Solution Approach 1:
Multiple smaller dies can be configured in different arrangements and combinations, enabling scalable processor designs. The interconnect architecture allows these segmented dies to work together as a unified system with monolithic cache domain, providing flexibility in processor configuration while maintaining design simplicity through standardized interconnection interfaces.
3Reliability
If multiple physically separate dies are connected, then yield risk is reduced and scalability is enhanced, but communication bandwidth and latency across die boundaries become critical
Solution Approach 1:
The patent merges multiple physically separate dies into a unified processor system with a monolithic cache domain through an interconnect architecture. This combining allows the segmented dies to communicate with each other as if they were part of a single die, maintaining high bandwidth and low latency while enjoying the benefits of reduced yield risk and enhanced scalability.
4Device complexity
If fixed routing is used in mesh interconnect, then routing is simple to implement, but path diversity is limited
Solution Approach 1:
The mesh interconnect routing is made dynamic by allowing selection between fixed routing and diverse routing modes. The system can adaptively choose routing paths based on traffic conditions and requirements, providing path diversity for strongly ordered messages while maintaining the simplicity of fixed routing when appropriate. This dynamic adaptability resolves the contradiction between routing simplicity and path diversity.
Data Source
AI summary
Methods and apparatuses related to efficient fabric usage. One embodiment of a method comprises: decoding, by a first bridge device associated with a plurality of source fabric agents, a first plurality of packets received from the plurality of source fabric agents of an interconnect fabric comprising a plurality of vertical interconnects coupled to a plurality of horizontal interconnects, wherein decoding is to identify one or more destination fabric agents associated with a second bridge device; routing, by first routing circuitry, the first plurality of packets across the interconnect fabric to the second bridge device, the first routing circuitry to distribute the first plurality of packets across at least one of: multiple vertical interconnects of the plurality of vertical interconnects and multiple horizontal interconnects of the plurality of horizontal interconnects.