Interconnect Pattern With Orthogonal Dummy Metal Lines for Wafer Warpage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increasing complexity of interconnect structures in semiconductor manufacturing leads to stress-induced wafer warpage, particularly due to the integration of multiple metallization layers, which complicates the back-end-of-line (BEOL) process and affects the precision and reliability of semiconductor devices.

Innovation Solution

The implementation of a semiconductor structure with alternating directional arrangements of dummy metal lines in odd- and even-numbered metallization layers, where dummy metal lines in odd-numbered layers extend in one direction and those in even-numbered layers extend perpendicular to it, helps reduce tensile stress and stretching forces, thereby mitigating wafer warpage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multiple metallization layers are integrated to increase storage capacity and processing speed, then device functionality is improved, but wafer warpage increases due to stress accumulation

Engineering Contradiction:
Improvedevice functionalityVSAvoidwafer stability
Core Design Contradiction:
Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

The patent introduces dummy metal lines specifically designed to counteract the tensile stress generated by functional metal lines. These dummy lines act as stress compensators that convert the harmful stress-induced warpage into a beneficial balanced stress state, allowing multiple metallization layers to be integrated without compromising wafer stability.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent modifies the physical parameters of the metallization structure by adding dummy metal lines with specific geometries (different widths, lengths, and positions) to alter the stress distribution parameters. By changing these structural parameters, the overall stress balance is adjusted to prevent warpage while maintaining the functionality of the interconnect structure.

Inventive Principle:
Principle #35Parameter changes

2Stability of the object's composition

If dummy metal lines are added to reduce wafer warpage, then wafer stability is improved, but interconnect structure complexity increases

Engineering Contradiction:
Improvewafer stabilityVSAvoidinterconnect structure complexity
Core Design Contradiction:
Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The patent segments the metallization layers into functional metal lines and dummy metal lines with distinct roles. The dummy lines are further segmented and positioned in specific patterns (alternating directions in odd and even layers) to systematically manage stress without requiring complete redesign of the entire interconnect architecture.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy metal lines serve as intermediary elements that mediate between the functional interconnect requirements and the mechanical stability requirements. These intermediaries absorb and balance stress without interfering with the electrical functionality of the primary metal lines, thus reducing warpage without fundamentally complicating the interconnect's primary function.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stress or pressure

If dummy metal lines extend in alternating directions in odd- and even-numbered layers, then stress distribution is improved, but manufacturing precision requirements increase

Engineering Contradiction:
Improvestress distributionVSAvoidpattern alignment precision
Core Design Contradiction:
Stress or pressureVSManufacturing precision

Solution Approach 1:

The patent employs asymmetric positioning of dummy metal lines where odd-numbered layers have dummy lines extending in one direction while even-numbered layers have dummy lines extending perpendicular to that direction. This asymmetric alternating pattern creates a balanced three-dimensional stress distribution that counteracts warpage while providing a systematic manufacturing guideline.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20230352404A1Interconnect structure pattern
Publication Date: 2023.11.02 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20230352404A1 patent drawing
  • US20230352404A1 patent drawing
  • US20230352404A1 patent drawing

AI summary

The present disclosure describes a structure with a substrate, a circuit element, a first metallization layer, and a second metallization layer. The circuit element is formed on the substrate. The first metallization layer is disposed over the substrate and includes a first metal line electrically connected to the circuit element and first dummy metal lines extending along a first direction. The second metallization layer is disposed directly above the first metallization layer and includes a second metal line electrically connected to the first metal line and second dummy metal lines extending along a second direction. The second direction is perpendicular to the first direction.