Interconnect Patterning Layer Mitigates ILD Damage
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Solution Overview
Problem
Misalignment errors during the patterning of inter-level dielectric (ILD) layers in integrated chips can cause damage to the ILD, leading to reduced reliability and performance due to electrical shorts and increased capacitance between adjacent interconnects, which affects the overall operation of the chip.
Innovation Solution
The implementation of an interconnect patterning layer with a selective etching process that differentiates the etching rates of materials, allowing for the exposure of upper surfaces of interconnects without damaging the ILD layer, thereby mitigating misalignment errors and enhancing chip reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional patterning process is used to form interconnect openings in ILD layers, then the interconnect openings can be formed, but misalignment errors cause damage to the ILD layer leading to electrical shorts and increased capacitance
Solution Approach 1:
A mandrel structure is introduced as an intermediary element between the patterning process and the ILD layer. The mandrel serves as a sacrificial template that defines the interconnect opening pattern while protecting the underlying ILD layer from direct exposure to misaligned etching processes. After the interconnect openings are formed through the mandrel, the mandrel is removed, leaving precisely defined openings without ILD damage.
Solution Approach 2:
The mandrel structure is formed in advance before the interconnect opening formation process. This preliminary structure establishes the precise pattern and position for the interconnect openings, allowing subsequent etching to proceed with accurate alignment. The pre-formed mandrel prevents misalignment errors from affecting the ILD layer integrity.
2Ease of manufacture
If misalignment errors occur during ILD patterning, then interconnect openings may still be formed, but damage to the ILD layer increases capacitance between adjacent interconnects
Solution Approach 1:
The mandrel acts as a protective intermediary that prevents direct contact between the etching process and the ILD layer in areas where misalignment might cause damage. By confining the etching action to precisely defined regions through the mandrel structure, unwanted capacitance effects are eliminated while maintaining ease of manufacture.
3Manufacturing precision
If misalignment errors damage the ILD layer, then interconnect openings can be formed, but electrical shorts occur between adjacent interconnects
Solution Approach 1:
The mandrel structure provides a physical barrier that prevents etching damage to the ILD layer that would otherwise create electrical shorts. The mandrel ensures that etching is confined to the intended interconnect opening regions, maintaining the electrical isolation properties of the ILD layer while still allowing accurate opening formation.
Solution Approach 2:
The mandrel structure provides beforehand protection against potential etching damage to the ILD layer. By having this sacrificial protective layer in place before the etching process, any misalignment errors are absorbed by the mandrel rather than causing electrical shorts between interconnects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces ILD damage and improves the reliability and performance of integrated chips by maintaining the integrity of the ILD layer and reducing electrical shorts and capacitance between interconnects.
Implementation Method 1
an etch stop structure arranged on the first ILD layer and along a sidewall of the interconnect patterning layer
Data Source
AI summary
The present disclosure relates an integrated chip. The integrated chip may include a first interconnect and a second interconnect disposed within a first inter-level dielectric (ILD) layer over a substrate. A lower etch stop structure is disposed on the first ILD layer and a third interconnect is disposed within a second ILD layer that is over the first ILD layer. The third interconnect extends through the lower etch stop structure to contact the first interconnect. An interconnect patterning layer is disposed on the second interconnect and laterally adjacent to the lower etch stop structure.