Interconnect Opening Patterning With Multi-Layer Masks for Etch Precision
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling down of semiconductor devices presents challenges in forming precise interconnect structures due to issues with etching selectivity and byproduct formation during the patterning of interconnect openings, leading to under-etching and increased contact resistance.
Innovation Solution
A dual damascene process using a multi-layer mask comprising a titanium-containing mask layer over a tungsten-containing mask layer to improve etching selectivity and reduce non-volatile byproducts, thereby reducing line width roughness and under-etching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer mask is used for patterning interconnect openings, then the process is simpler, but etching selectivity is insufficient leading to under-etching and line width roughness
Solution Approach 1:
The mask structure is segmented into multiple layers: a first mask layer (e.g., silicon oxide) and a second mask layer (e.g., tungsten carbide) with different etching selectivities. This segmentation allows the first etch process to selectively remove the first mask layer while preserving the second mask layer, achieving precise patterning without under-etching.
Solution Approach 2:
The mask structure uses composite materials with different properties - the first mask layer material (silicon oxide) and second mask layer material (tungsten carbide) have different etching rates and physical properties. This composite approach enables differential etching to achieve precise interconnect opening formation while maintaining mask integrity.
2Productivity
If conventional etching processes are used, then the process is faster, but non-volatile byproducts accumulate increasing contact resistance
Solution Approach 1:
The patent converts the potentially harmful byproduct formation into a beneficial process feature. By selecting specific etchant chemistry that reacts with the mask layers to form volatile byproducts, the process eliminates non-volatile residue accumulation. The controlled reaction produces gaseous byproducts that are easily removed, preventing contact resistance issues.
3Manufacturing precision
If mask layer thickness is increased to improve patterning, then etching selectivity improves, but line width roughness increases
Solution Approach 1:
Different regions of the mask structure have different thicknesses optimized for their specific functions. The first mask layer has a thickness optimized for selective removal, while the second mask layer has a thickness optimized for pattern definition. This local optimization of thickness at different mask layers achieves both high etching selectivity and smooth line width.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enhances the precision of interconnect formation by minimizing line width roughness and under-etching, improving device performance and reducing contact resistance.
Implementation Method 1
The etchant selectively reacts with the first mask layer material to form a first byproduct that has a boiling point less than the process temperature
Implementation Method 2
The first byproduct has a boiling point less than the process temperature, allowing selective removal without residue
Implementation Method 3
The etchant also reacts with the second mask layer material to form a second byproduct that has a boiling point greater than the process temperature
Data Source
AI summary
A method includes depositing a first dielectric layer over a first conductive feature, depositing a first mask layer over the first dielectric layer, and depositing a second mask layer over the first mask layer. A first opening is patterned in the first mask layer and the second mask layer, the first opening having a first width. A second opening is patterned in a bottom surface of the first opening, the second opening extending into the first dielectric layer, the second opening having a second width. The second width is less than the first width. The first opening is extended into the first dielectric layer and the second opening is extended through the first dielectric layer to expose a top surface of the first conductive feature.