Semiconductor Interconnect Patterning with Spacers and Line Cuts

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Solution Overview

Problem

As semiconductor devices continue to shrink, traditional photolithography equipment struggles to achieve the desired pitch and accuracy for manufacturing, leading to manufacturing challenges and increased costs due to difficulties in aligning etch masks and maintaining precise patterns.

Innovation Solution

A patterning process involving the use of spacers and a sacrificial material to pattern an underlying mask layer, which is then used to pattern a target layer in a single step, allowing for the formation of fine pitch interconnect lines with line cuts, reducing manufacturing complexity and increasing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If traditional photolithography equipment is used, then manufacturing process is simpler, but manufacturing precision deteriorates due to inability to achieve desired pitch and alignment accuracy

Engineering Contradiction:
Improvepitch and alignment accuracyVSAvoidpatterning process complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patterning process is divided into multiple stages: forming mandrels, depositing spacers, removing mandrels, and forming sacrificial material. Each stage achieves a specific function, collectively enabling fine pitch patterning that exceeds traditional photolithography capabilities while maintaining process manageability through modular steps

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Spacer material and sacrificial material are introduced as intermediary elements. The spacers serve as temporary structures that define the final pattern geometry, while the sacrificial material is used to create line cuts. These intermediaries enable precise pattern transfer without requiring direct photolithography at the target pitch scale

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If multiple patterning steps are used to achieve fine pitch, then manufacturing precision improves, but manufacturing time and complexity increase

Engineering Contradiction:
Improvepattern accuracyVSAvoidmanufacturing cycle time
Core Design Contradiction:
Manufacturing precisionVSLoss of time

Solution Approach 1:

The spacer structures are formed in advance with precise dimensions through conformal deposition. This preliminary structuring establishes the final pattern geometry before etching, eliminating the need for multiple alignment steps and reducing overall manufacturing cycle time while maintaining high precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Multiple functions are combined into single process steps where possible. For example, the spacer formation simultaneously defines feature pitch and serves as an etch mask. The sacrificial material formation combines line cut definition with pattern transfer, reducing the number of separate processing steps required

Inventive Principle:
Principle #5Merging (Combining)

3Length of moving object

If photolithography is pushed to theoretical limits, then pitch reduction is achieved, but reliability deteriorates due to process window narrowing

Engineering Contradiction:
Improvefeature sizeVSAvoidprocess robustness
Core Design Contradiction:
Length of moving objectVSReliability

Solution Approach 1:

The patent replaces optical lithography with a deposition-based self-aligned patterning approach. Conformal spacer deposition and anisotropic etching create patterns with dimensions determined by film thickness and etch selectivity rather than optical resolution, achieving smaller features with larger process windows and improved robustness

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patterning mechanism transitions from optical parameter control (wavelength, numerical aperture) to material parameter control (film thickness, deposition conformality, etch selectivity). This parameter transformation enables precise feature size control through physical dimensions of deposited layers rather than optical diffraction limits, improving process reliability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12002711B2Patterning methods for semiconductor devices and structures resulting therefrom
Publication Date: 2024.06.04 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US12002711B2 patent drawing
  • US12002711B2 patent drawing
  • US12002711B2 patent drawing

AI summary

Semiconductor devices and methods of forming semiconductor devices are provided. A method includes forming a first mask layer over a target layer, forming a plurality of spacers over the first mask layer, and forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, where in a plan view a major axis of the opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers. The method also includes depositing a sacrificial material in the opening, patterning the sacrificial material, etching the first mask layer using the plurality of spacers and the patterned sacrificial material, etching the target layer using the etched first mask layer to form second openings in the target layer, and filling the second openings in the target layer with a conductive material.