Multi-Lane Interconnect PHY for Blocking Link State Transitions
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Solution Overview
Problem
The increasing demand for high-performance computing has outpaced the capabilities of existing interconnect architectures, particularly in server systems, where communication between multiple processors and devices is critical but often bottlenecked by traditional interconnects.
Innovation Solution
A high-performance interconnect (HPI) architecture is introduced, featuring a layered protocol stack with point-to-point links, coherent cache protocols, and embedded clock signaling to enhance data transfer efficiency and reduce latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for interconnect, then device complexity is reduced, but data transfer speed and communication performance deteriorate
Solution Approach 1:
The interconnect architecture is segmented into multiple point-to-point links instead of a single shared bus. Each link connects specific devices (e.g., processor to memory controller, memory controller to storage) with dedicated communication paths, eliminating the need for complex arbitration and multiplexing while enabling simultaneous high-speed transfers across multiple channels.
Solution Approach 2:
The interconnect transitions from a one-dimensional shared bus to a multi-dimensional hierarchical structure with multiple layers (e.g., Level 1 cache interconnect, Level 2 cache interconnect, memory controller interconnect). This dimensional expansion allows parallel communication paths operating at different speeds and granularities, significantly increasing aggregate bandwidth without proportionally increasing complexity.
2Productivity
If more processors and devices are added to increase computing power, then processing capability improves, but communication bottleneck between sockets worsens
Solution Approach 1:
The communication infrastructure is segmented into multiple dedicated point-to-point links distributed across different hierarchy levels. Each processor socket has direct access to multiple memory controllers and caches through separate high-speed links, eliminating the shared bus bottleneck and enabling parallel communication paths that scale with the number of processors.
Solution Approach 2:
The interconnect architecture implements dynamic resource allocation and adaptive routing where communication paths can be dynamically adjusted based on workload requirements. The system can dynamically activate additional communication channels when needed and optimize data routing in real-time, allowing the communication infrastructure to scale flexibly with computing power demands.
3Speed
If higher data transfer rates are demanded, then performance improves, but power consumption increases
Solution Approach 1:
The data transfer path is segmented into multiple parallel channels (e.g., multiple lanes in a PCIe-like interface or multiple point-to-point links). Instead of increasing the bandwidth of a single channel, the system aggregates multiple narrower channels to achieve the required total data transfer rate, reducing the power consumption per channel while maintaining high overall throughput.
Solution Approach 2:
The interconnect system dynamically adjusts the number of active communication channels and data transfer rates based on actual workload requirements. When high data transfer rates are needed, the system activates additional channels and increases individual channel speeds; when bandwidth demand is lower, the system reduces the number of active channels and operates at lower speeds, thereby optimizing power consumption.
Data Source
AI summary
A physical layer (PHY) is coupled to a serial, differential link that is to include a number of lanes. The PHY includes a transmitter and a receiver to be coupled to each lane of the number of lanes. The transmitter coupled to each lane is configured to embed a clock with data to be transmitted over the lane, and the PHY periodically issues a blocking link state (BLS) request to cause an agent to enter a BLS to hold off link layer flit transmission for a duration. The PHY utilizes the serial, differential link during the duration for a PHY associated task selected from a group including an in-band reset, an entry into low power state, and an entry into partial width state.