Interconnect PHY Link Training With EIEOS Latency Alignment
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in meeting the increasing demand for bandwidth and power efficiency, particularly in servers and mobile devices, as they become more complex and require higher performance with minimal power consumption.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that includes a layered protocol stack with a transaction layer, link layer, and physical layer, along with features like credit-based flow control, virtual channels, and power management, to enable efficient data transfer and power optimization across multiple devices and processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional multi-drop buses are used for electrical communications, then device complexity is reduced, but communication performance and bandwidth are insufficient
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links instead of a shared multi-drop bus. Each link connects specific devices directly, enabling parallel communication paths and eliminating bus contention, thereby improving communication performance while maintaining manageable complexity through modular link design
Solution Approach 2:
The architecture transitions from a one-dimensional shared bus to a multi-dimensional interconnected graph of point-to-point links. This dimensional expansion allows simultaneous communication across multiple paths, significantly increasing bandwidth and communication throughput without proportionally increasing complexity
2Productivity
If processing power and number of devices are increased, then computing capability is improved, but power consumption increases
Solution Approach 1:
The system implements periodic link training and state transitions where interconnect links can enter low-power states when not actively transmitting data. Links are activated only when needed for specific communication transactions, enabling the system to maintain high computing capability while reducing overall power consumption through periodic activation of interconnect resources
Solution Approach 2:
The interconnect architecture dynamically adjusts transmission parameters such as data rate, link width, and power supply levels based on actual communication needs. When bandwidth demands are low, the system reduces operating frequency and power delivery to interconnect components, maintaining computing capability when needed while optimizing power consumption during idle or low-activity periods
3Speed
If interconnect bandwidth is increased to meet demand, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The interconnect links implement dynamic rate matching where each link can operate at different data rates depending on the bandwidth requirements of connected devices and current traffic conditions. This dynamic adjustment allows the system to provide high data transfer speeds when needed while reducing power consumption during low-bandwidth periods, optimizing the trade-off between speed and energy usage
Data Source
AI summary
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.