Interconnect Physical Layer Re-Initialization Across Multi-Lane Links
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Solution Overview
Problem
Current interconnect architectures in high-performance computing systems face challenges in efficiently managing communication between multiple processors and devices, particularly in meeting the increasing demand for bandwidth and power efficiency across various market segments, including servers and mobile devices.
Innovation Solution
The development of a High Performance Interconnect (HPI) architecture that incorporates a layered protocol stack, including a transaction layer, link layer, and physical layer, with features such as credit-based flow control, virtual channels, and embedded clock signaling, to facilitate efficient data transfer and power management across point-to-point links.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional multi-drop buses are used for electrical communications, then device compatibility is maintained, but communication speed and bandwidth are insufficient
Solution Approach 1:
The interconnect architecture is segmented into multiple independent point-to-point links rather than using a shared multi-drop bus. Each link connects specific devices directly, enabling parallel communication paths that increase overall bandwidth and communication speed without requiring complex arbitration protocols.
Solution Approach 2:
The patent transitions from a one-dimensional shared bus architecture to a multi-dimensional point-to-point link architecture with multiple lanes and hierarchical levels. This dimensional expansion allows simultaneous data transmission across multiple paths, dramatically increasing communication capacity while maintaining manageable complexity through modular design.
2Productivity
If processing power is increased with multiple sockets, then computing capability improves, but communication demand between sockets increases
Solution Approach 1:
The point-to-point interconnect links serve multiple functions simultaneously: they transmit data, carry error correction codes, support flow control, and enable power management. This multi-functionality allows the system to handle increased communication traffic from multiple sockets without requiring separate dedicated channels for each function, thereby supporting higher computing power with efficient communication.
3Productivity
If data transfer speed is increased, then bandwidth demand is met, but power consumption increases
Solution Approach 1:
The interconnect architecture implements dynamic power management where links can be selectively activated or deactivated based on actual communication needs. Flow control mechanisms dynamically adjust data transmission rates and enable/disable power delivery to individual links, allowing the system to maintain high data transfer rates when needed while significantly reducing power consumption during idle or low-activity periods.
Data Source
AI summary
Re-initialization of a link can take place without termination of the link, where the link includes, a transmitter and a receiver are to be coupled to each lane in the number of lanes, and re-initialization of the link is to include transmission of a pre-defined sequence on each of the lanes.