Variable-Height Interconnect Pillars for Die Warpage Compensation

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Solution Overview

Problem

Individual dies in a stack of dies often experience warpage issues due to differences in material choices and processing conditions, which can lead to misalignment and connectivity problems in memory devices.

Innovation Solution

The use of interconnect pillars with varying heights and diameters is implemented to accommodate different warpage profiles across dies, ensuring proper alignment and connectivity by mapping pillar height distributions to known warpage profiles, and employing materials like copper, nickel, and solder for the pillars.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If uniform interconnect pillars are used across all dies, then manufacturing process is simple, but warpage causes misalignment and connectivity problems

Engineering Contradiction:
Improveconnectivity reliabilityVSAvoidinterconnect pillar structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies local quality by varying interconnect pillar heights and diameters based on local warpage conditions. Different regions of the die stack receive pillars with specifically tailored dimensions to compensate for local warpage deviations, ensuring uniform contact pressure and reliable connectivity across the entire stacked memory device.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements parameter changes by adjusting interconnect pillar height and diameter as compensation variables. By mapping measured warpage profiles to corresponding pillar dimension parameters, the system dynamically modifies pillar geometry to counteract warpage effects, transforming a uniform structure into a compensated non-uniform structure that maintains connectivity reliability.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If die warpage is not compensated, then manufacturing process is simple, but alignment precision deteriorates

Engineering Contradiction:
Improvedie alignment precisionVSAvoidmanufacturing process complexity
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent applies preliminary action by measuring and mapping die warpage profiles before interconnect pillar formation, then using this pre-acquired warpage data to determine optimal pillar height and diameter distributions. This advance compensation planning enables precise alignment to be built into the manufacturing process rather than requiring post-assembly adjustment.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent replaces mechanical alignment adjustment mechanisms with a design-based compensation approach. Instead of using adjustable mechanical fixtures or post-assembly alignment procedures, the system substitutes a predetermined non-uniform pillar geometry design that passively compensates for warpage, simplifying the manufacturing process while maintaining high alignment precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Manufacturing precision

If interconnect pillars are made taller to accommodate warpage, then alignment tolerance increases, but device height and complexity increase

Engineering Contradiction:
Improvealignment toleranceVSAvoidinterconnect pillar height
Core Design Contradiction:
Manufacturing precisionVSLength of stationary object

Solution Approach 1:

The patent applies local quality by selectively increasing pillar height only in regions where warpage requires additional compensation, rather than uniformly increasing all pillar heights. This localized height variation provides necessary alignment tolerance where needed while minimizing overall device height increase and structural complexity.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent implements asymmetry by creating a non-uniform pillar height distribution that mirrors the asymmetric warpage profile of the die stack. This asymmetric pillar configuration provides targeted alignment tolerance in high-warpage regions while maintaining compact dimensions in low-warpage regions, optimizing the trade-off between alignment capability and device size.

Inventive Principle:
Principle #4Asymmetry

Data Source

PatentUS20240071972A1Semiconductor conductive pillar device and method
Publication Date: 2024.02.29 MICRON TECHNOLOGY INC
  • US20240071972A1 patent drawing
  • US20240071972A1 patent drawing
  • US20240071972A1 patent drawing

AI summary

Apparatus and methods are disclosed, including stacked die devices and systems. Example stacked die devices and methods include an array of interconnect pillars that includes more than one pillar height. Example stacked die devices and methods include an array of interconnect pillars that includes a pillar height distribution mapped to a known warpage profile.