Interconnect Structure With Planarization Stop Layer for Via Loss
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Solution Overview
Problem
The formation of interconnect structures in semiconductor devices is challenged by via loss and IMD dishing, which occur during planarization operations, leading to unreliable connections and increased short-circuit risks due to the difficulty in stopping the planarization process at the correct height of low-density top vias.
Innovation Solution
A semiconductor device with a base layer and interconnect structure that includes a planarization stop layer formed in an isolation layer, allowing for two planarization operations to prevent via loss and IMD dishing, comprising a metal line, a top via protruded from the metal line without a connection surface, and an isolation layer with a planarization stop layer vertically and laterally positioned.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single planarization operation is performed on the IMD layer, then the planarization process can be completed in one step, but via loss and IMD dishing occur leading to unreliable connections
Solution Approach 1:
The single planarization operation is divided into two separate planarization operations. The first planarization operation planarizes the first IMD layer, and the second planarization operation planarizes the second IMD layer. This segmentation allows each operation to be optimized independently, preventing via loss and IMD dishing while maintaining overall process efficiency.
Solution Approach 2:
The first planarization operation is performed as a preliminary action before forming the metal lines and vias in the second IMD layer. This preliminary planarization ensures a flat surface for subsequent processing, preventing via loss and dishing issues that would compromise connection reliability.
2Manufacturing precision
If the planarization process continues until the metal line level is exposed, then complete planarization is achieved, but top vias are lost due to over-planarization
Solution Approach 1:
The first planarization operation is performed preliminarily to expose the metal line level without removing the top vias. This controlled preliminary planarization achieves the necessary flatness for subsequent processing while preserving the top vias for reliable connections.
Solution Approach 2:
Instead of performing excessive planarization that would remove the top vias, the process uses partial planarization in the first operation to achieve the required surface flatness. The second planarization operation then completes the planarization safely without risking via loss.
3Manufacturing precision
If planarization is performed on low-density top vias, then the vias can be planarized, but it is difficult to stop at the correct height leading to via loss
Solution Approach 1:
The planarization of low-density top vias is segmented into two operations. The first operation planarizes to a controlled height that preserves the vias, and the second operation completes the planarization. This segmentation makes it easier to control the planarization depth and avoid via loss.
Solution Approach 2:
The first planarization operation serves as a preliminary step that planarizes the surface to a height that exposes the metal lines but preserves the top vias. This preliminary planarization establishes a safe stopping point that prevents via loss while achieving necessary surface flatness.
Data Source
Figure 1A
Figure 1B~1C
Figure 2~3
AI summary
Provided is a semiconductor device including a base layer and an interconnect structure on the base layer, the interconnect structure including: a 1st metal line on the base layer; a 1st top via vertically protruded from the 1st metal line without a connection surface therebetween; an isolation layer on the 1st metal line and the 1st top via; and a planarization stop layer vertically and laterally on the isolation layer.