Interconnect Plating Layout for Better CMP Planarization
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving reliable formation of interconnect features during IC fabrication due to excessive metal loading outside opening areas during metal plating, leading to uneven surfaces, reduced CMP efficiency, and increased fabrication costs.
Innovation Solution
A method involving the deposition and patterning of a photoresist/BARC layer on the semiconductor substrate, which creates a conductivity difference between opening areas and other areas, allowing for high plating speed in openings and low plating speed elsewhere, thereby reducing metal loading and improving global planarization during the CMP process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If metal plating is performed without conductivity control, then plating speed is high, but metal loading outside opening areas becomes excessive
Solution Approach 1:
The patent applies local quality by creating different conductivity conditions in different areas of the substrate. The photoresist/BARC layer is selectively removed from opening areas while retained in non-opening areas, resulting in high conductivity (and thus high plating speed) only in opening areas, and low conductivity (and thus low plating speed) in non-opening areas. This spatial variation in material properties resolves the contradiction by enabling fast plating where needed while preventing excessive metal deposition where not needed.
Solution Approach 2:
The patent uses the photoresist/BARC layer as an intermediary substance that mediates the plating process. This layer acts as a conductivity modifier that can be selectively present or absent to control metal deposition. By using this intermediary, the process achieves differential plating rates without requiring direct mechanical or electrical control of each plating location, thus resolving the contradiction between plating speed and metal loading control.
2Speed
If metal plating is performed without conductivity control, then plating speed is high, but surface uniformity deteriorates
Solution Approach 1:
The patent creates local quality differences in conductivity across the substrate surface. By selectively removing the photoresist/BARC layer from opening areas while maintaining it in non-opening areas, the process achieves high plating speed in openings (where conductivity is high) while preventing excessive deposition in non-openings (where conductivity is low). This results in uniform surfaces with proper metal fill in openings and controlled minimal deposition elsewhere, resolving the contradiction between speed and surface uniformity.
3Productivity
If conventional plating and CMP processes are used, then interconnect features are formed, but CMP efficiency is reduced due to uneven surfaces
Solution Approach 1:
The patent applies preliminary action by controlling the metal plating process to pre-establish uniform surface conditions before the CMP step. By using conductivity-controlled plating to achieve uniform metal deposition patterns (full fill in openings, controlled deposition elsewhere), the subsequent CMP process operates on a more uniform surface, significantly improving CMP efficiency and reducing the time and resources needed for planarization.
4Quantity of substance
If conventional plating processes are used, then metal deposition is achieved, but fabrication costs increase
Solution Approach 1:
The patent reduces fabrication costs by applying local quality control to the metal deposition process. By ensuring high metal deposition only in opening areas where it is needed for interconnect formation, and minimizing deposition in non-opening areas, the process reduces overall metal consumption. Additionally, the improved surface uniformity reduces CMP processing requirements, further lowering fabrication costs while maintaining necessary metal deposition in critical areas.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances global planarization, improves within-wafer and within-die loading, and reduces fabrication costs by controlling metal plating speeds and optimizing the CMP process.
Implementation Method 1
depositing a photoresist and a BARC layer on the semiconductor substrate, wherein the photoresist and the BARC layer create a conductivity difference between opening areas and other areas
Implementation Method 2
depositing, via an electroplating process, a conductive material in the opening
Implementation Method 3
Metal plating and chemical mechanical polishing (CMP) are two important processes for forming the interconnect features during IC fabrication. The CMP process combines chemical removal with mechanical polishing.
Data Source
AI summary
The present disclosure relates to a method of forming an interconnect structure. The method can include providing a semiconductor substrate; depositing a photoresist and a BARC layer on the semiconductor substrate; forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate; depositing a conductive material to fill the opening; and planarizing the conductive material and the semiconductor substrate.