Interconnect Structure Plating Process for Fine Pitch Resolution
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Solution Overview
Problem
Conventional interconnect structures in semiconductor devices require etching processes, which are time-consuming and may not achieve fine pitch interconnects due to the need for etch stop layers and recesses in metal lines.
Innovation Solution
The formation of metal lines and vias in a dual damascene structure without an etching step, using a plating process that eliminates the need for etch stop layers and allows direct contact between the dual damascene structure and the metal lines, enabling improved resolution and reduced production time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional etching processes are used to form interconnect structures, then the manufacturing process is well-established and reliable, but the production time increases and fine pitch interconnects cannot be achieved due to etch stop layers and metal line recesses
Solution Approach 1:
The patent removes the etching step entirely from the interconnect formation process. Instead of using conventional etching methods that require etch stop layers and create metal line recesses, the invention directly forms metal lines and vias through a plating process, extracting the harmful etching operation from the manufacturing sequence.
Solution Approach 2:
The patent replaces the mechanical/chemical etching process with an electrochemical plating process. The plating process uses electrical current to deposit metal directly onto the substrate, forming interconnect structures without the need for mechanical removal of material through etching, thereby eliminating etch stop layers and recesses.
2Manufacturing precision
If etch stop layers are used in conventional interconnect formation, then the etching process can be controlled and stopped at precise depths, but the device complexity increases and fine pitch interconnects cannot be achieved
Solution Approach 1:
The patent extracts and removes the etch stop layer from the interconnect structure. By eliminating the etching process entirely, the need for etch stop layers to control etch depth is removed, simplifying the overall device structure while maintaining the ability to form precise interconnect features through direct plating.
Solution Approach 2:
The patent replaces the etch stop layer mechanism with a direct plating approach. Instead of using a sacrificial etch stop layer to control depth, the plating process directly forms the metal interconnects to the required depth and dimensions, eliminating the additional layer and simplifying the structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces production time and enhances the resolution of interconnect structures, allowing for the creation of fine pitch interconnects without the need for etch stop layers, thereby improving the efficiency and precision of semiconductor device fabrication.
Implementation Method 1
an electroplating process may be applied to the dual damascene opening. As a result, the dual damascene opening is filled with a conductive material
Data Source
AI summary
An apparatus comprises an interlayer dielectric layer formed on a first side of a substrate, a first photo-sensitive dielectric layer formed over the interlayer dielectric layer, wherein the first photo-sensitive dielectric layer comprises a first metal structure and a second photo-sensitive dielectric layer formed over the first photo-sensitive dielectric, wherein the second photo-sensitive dielectric layer comprises a second metal structure having a bottom surface coplanar with a top surface of the first metal structure.