Interconnect Protection Scheme Conversion for Heterogeneous SoCs
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Solution Overview
Problem
Systems-on-chips (SoCs) face challenges in connecting IPs with inherently incompatible error protection schemes, requiring a method to enable communication and conversion between different protection schemes, especially in interconnects within SoCs.
Innovation Solution
An encoder unit is used to receive redundant information according to one scheme and encode it into another scheme, allowing for communication between IPs with different protection schemes, and includes mechanisms for consistency checking and error handling within the interconnect, enabling conversion between various protection schemes such as parity and ECC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different IPs use different protection schemes (e.g., 32-bit SECDED ECC for CPU, 128-bit SECDED ECC for Flash controller), then each IP can operate with its own optimized error protection, but the IPs cannot be properly connected in an SoC due to incompatibility
Solution Approach 1:
The patent introduces an interconnect IP as an intermediary component between heterogeneous IPs with different protection schemes. This interconnect IP includes conversion logic that translates data packets from one protection scheme to another, enabling communication between IPs that would otherwise be incompatible. For example, it can convert between 32-bit SECDED ECC and 128-bit SECDED ECC schemes, allowing the CPU and Flash controller to communicate despite using different error protection standards.
Solution Approach 2:
The interconnect IP dynamically changes parameters such as data width, protection scheme type, and packet format to accommodate different IPs. The system can configure the interconnect to use different data bus widths (e.g., 32-bit, 64-bit, 128-bit) and switch between various protection schemes (parity, ECC, SECDED) based on the connected IPs requirements, thereby achieving versatility while maintaining reliability.
2Adaptability or versatility
If an interconnect IP is made configurable as HDL code to connect IPs with incompatible protection schemes, then interconnect compatibility improves, but device complexity increases
Solution Approach 1:
The interconnect IP is designed as a universal component that can handle multiple protection schemes and data widths through a single configurable architecture. Rather than creating separate interconnect instances for each IP pair, the universal interconnect can be configured via HDL parameters to work with any combination of IPs, reducing overall system complexity while maintaining high adaptability.
Solution Approach 2:
The interconnect IP employs dynamic configuration capabilities where protection scheme parameters, data widths, and packet formats can be adjusted at runtime or during system initialization. This dynamic adaptability allows the same hardware structure to serve multiple purposes, reducing the need for multiple specialized components and simplifying the overall system design.
3Adaptability or versatility
If data changes within the interconnect (e.g., serialization changes, firewall modifications), then the interconnect can adapt to different data formats, but correctness must be checked and redundant information recalculated
Solution Approach 1:
The interconnect IP performs preliminary error checking and validation before data modification operations. When data undergoes serialization changes or firewall modifications, the system pre-calculates the expected redundant information and validates it against the modified data, ensuring correctness is maintained throughout the transformation process.
Solution Approach 2:
The system implements feedback mechanisms where error checkers continuously monitor data integrity after modifications. If correctness checks fail or redundant information becomes invalid due to data changes, the feedback loop triggers recalculation of the redundant information or error correction procedures, thereby maintaining reliability despite format flexibility.
Data Source
AI summary
Systems-on-chip are designed with different IPs that use different data protection schemes. Modules are used between the IPs, and the modules convert between protection schemes. Protection schemes can be per-byte, word, packet, flit, or burst. Conversion can involve splitting, merging, encapsulation, conversion, and generation of redundant information. Encoding of redundancy according to protection schemes can occur directly at an IP interface or within an interconnect, such as within a packet-based NoC. Designs include SoCs, hardware description language code describing functions within SoCs, and non-transient computer readable media that store such source code.