Interconnect Structure With Dielectric Protrusions Against CMP Dishing
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Solution Overview
Problem
The existing semiconductor manufacturing techniques face challenges in reducing the dishing phenomenon in low device density regions or large linewidth regions during the polishing process of interconnect structures, which affects the quality of the interconnects.
Innovation Solution
The introduction of a dielectric layer with protrusions that are strategically arranged to intersect any straight path crossing the central region, effectively blocking the dishing path and reducing the dishing phenomenon by providing resistance to polishing pressure across 360 degrees.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a polishing process is used to manufacture interconnect structures, then the interconnect structures can be formed with copper material, but dishing phenomenon occurs in low device density regions or large linewidth regions, reducing the quality of the interconnect structures
Solution Approach 1:
The patent applies preliminary action by forming protrusions on the dielectric layer surface before the polishing process. These protrusions are strategically positioned to intersect any straight path crossing the central region, creating a pre-configured structure that prevents dishing during subsequent polishing operations. The protrusions are formed as part of the dielectric layer fabrication sequence, enabling the polishing process to proceed without causing dishing in low device density regions.
Solution Approach 2:
The patent implements local quality by creating non-uniform surface features (protrusions) only in specific regions where dishing is likely to occur. The protrusions are distributed to intersect any straight path crossing the central region, providing localized resistance to polishing pressure exactly where needed, while leaving other regions unaffected. This targeted approach maintains interconnect thickness uniformity without unnecessarily complicating the entire structure.
2Adaptability or versatility
If the linewidth of interconnect structures is increased in low device density regions, then the interconnect structures can accommodate lower device density, but the copper material is more prone to dishing, reducing interconnect quality
Solution Approach 1:
The patent applies local quality by introducing protrusions specifically in low device density regions where large linewidths are used. The protrusions are distributed to intersect any straight path crossing the central region, providing localized resistance to polishing pressure in these vulnerable areas. This allows the interconnect structure to adapt to varying device density requirements while maintaining thickness uniformity through the strategically placed protrusions.
Solution Approach 2:
The patent uses preliminary anti-action by pre-forming protrusions that will counteract the dishing force during polishing. These protrusions are positioned to intersect any straight path crossing the central region, creating a preliminary structural barrier that prevents the polishing pressure from causing dishing in large linewidth regions. The protrusions are formed before polishing, enabling them to resist the upcoming harmful effect.
Data Source
AI summary
An interconnect structure is formed on a substrate in a semiconductor device. The interconnect structure includes a dielectric layer and a metal layer. The dielectric layer includes a region and a plurality of protrusions. The metal layer is disposed on the region and between the protrusions, wherein tops of the protrusions are exposed with respect to the metal layer. In a top view of the semiconductor device, the protrusions are distributed in the region. Any straight path crossing through a central region of the region is always intersected with a portion of the protrusions.