Interconnect Recess Vertical Clearance for Misalignment Tolerance
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Solution Overview
Problem
The challenge in microelectronic device fabrication is the misalignment of interconnect features between upper and underlying layers, leading to unintended electrical shorting due to scaling limitations, which reduces the margin for shift without increasing the pitch of interconnect features.
Innovation Solution
The solution involves forming a bottom interconnect feature within a recess in the bottom dielectric material with a vertical clearance, followed by depositing a conformal layer and a top dielectric material, allowing for the formation of top interconnect features that can shift laterally without electrical shorting, as the vertical clearance maintains separation even if the top features are close to the bottom ones.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If interconnect features are scaled down to reduced pitch, then device density and integration are improved, but misalignment between layers occurs leading to electrical shorting
Solution Approach 1:
The patent introduces a vertical recess structure into the bottom dielectric material, creating a three-dimensional configuration. The interconnect feature is positioned within this recess at a lower elevation, establishing a vertical height difference (clearance) between the bottom interconnect feature and the top interconnect layer. This dimensional change from planar to vertical spacing provides misalignment tolerance without requiring tighter lateral control.
Solution Approach 2:
The recess structure acts as an intermediary element between the bottom interconnect feature and the top interconnect layer. By introducing this intermediate vertical structure, the patent mediates the alignment relationship between the two layers, allowing lateral shifts without direct contact. The recess serves as a buffer zone that decouples the lateral positioning requirements of adjacent layers.
2Reliability
If lateral margin for shift is increased to prevent shorting, then reliability is improved, but pitch of interconnect features must increase reducing device density
Solution Approach 1:
The patent resolves this contradiction by transitioning the spacing mechanism from lateral to vertical dimension. Instead of increasing lateral pitch to prevent shorting, the invention creates vertical clearance through the recess structure. The bottom interconnect feature sits lower in the recess, providing vertical separation from the top interconnect layer, thereby maintaining tight lateral pitch while ensuring reliable isolation even with lateral shifts.
Solution Approach 2:
The recess structure creates a localized region with different geometric properties. Within the recess, the bottom interconnect feature has a lower top surface elevation, creating a localized vertical clearance zone. This local geometric modification provides misalignment tolerance specifically where needed, without requiring global increases in pitch across the entire interconnect structure.
3Manufacturing precision
If vertical clearance is created by forming recess, then manufacturing complexity increases, but alignment tolerance is improved
Solution Approach 1:
The recess structure is formed in advance, before the top interconnect layer is deposited. This preliminary creation of the vertical clearance structure allows subsequent layers to be formed with standard processes. By pre-establishing the vertical geometry, the patent enables later alignment tolerance without requiring complex real-time adjustment processes during top layer formation.
Solution Approach 2:
The patent segments the dielectric material to create the recess structure. By dividing the bottom dielectric into regions with and without recesses, the invention creates localized vertical clearance zones. This segmentation approach allows the complex three-dimensional structure to be formed using standard lithography and etching processes applied to patterned regions, rather than requiring entirely new manufacturing techniques.
Data Source
AI summary
An integrated circuit device includes a first interconnect layer, and a second interconnect layer above the first interconnect layer. The first interconnect layer includes (i) a first dielectric material, (ii) a recess within the first dielectric material, and (iii) a first interconnect feature within the recess. In an example, a top surface of the first interconnect feature is at least 1 nanometer (nm), or at least 3 nm, or at least 5 nm below a top surface of the first dielectric material. The second interconnect layer includes (i) a second dielectric material, and (ii) a second interconnect feature within the second dielectric material. In an example, the second interconnect feature is at least in part above, and conductively coupled to, the first interconnect feature. In an example, a bottom section of the second interconnect feature is within a top section of the recess.