Coherent Interconnect Recovery via Protocol Layer Re-transmission

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Solution Overview

Problem

Existing multi-processor data processing systems face challenges in maintaining cache coherence and fault tolerance due to issues like silent data corruption, inconsistent memory operations, and message loss in their coherence protocols.

Innovation Solution

A protocol layer re-transmission mechanism is introduced to provide fault tolerance by extending existing coherent protocols with error-resilient response packets at selective points in the transaction flow, incorporating acknowledgement and negative-acknowledgement messages to detect and recover from errors, and implementing snoop and request replay to reduce recovery latency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a coherence protocol is used to ensure data consistency across processors, then cache coherence is improved, but the system becomes vulnerable to silent data corruption and message loss

Engineering Contradiction:
Improvecache coherenceVSAvoidsilent data corruption
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent implements acknowledgment messages that provide feedback between nodes to confirm successful message delivery. When a node sends a coherence protocol message, it waits for an acknowledgment from the receiving node. If no acknowledgment is received or a negative acknowledgment is received indicating an error, the sending node retransmits the message, thereby preventing silent data corruption while maintaining cache coherence.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent incorporates error detection mechanisms and acknowledgment protocols before proceeding with data operations. Nodes verify message integrity and confirm receipt beforehand, ensuring that coherence operations are performed on valid, non-corrupted data, thus preventing silent data corruption while maintaining system reliability.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If error detection and re-transmission mechanisms are added to the coherence protocol, then fault tolerance is improved, but protocol complexity increases

Engineering Contradiction:
Improvefault toleranceVSAvoidprotocol complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines error detection, acknowledgment, and retransmission mechanisms with the existing coherence protocol into a unified message exchange framework. Rather than adding separate complex error handling systems, the error tolerance features are integrated into the standard coherence message flow, allowing nodes to handle both coherence management and error recovery using the same protocol infrastructure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent implements automatic retransmission at the node level without requiring external intervention or complex centralized error management. When a node detects an error or fails to receive an acknowledgment, it autonomously retransmits the message according to the protocol rules, simplifying the overall system architecture while improving fault tolerance.

Inventive Principle:
Principle #25Self-service

3Reliability

If acknowledgment messages are sent for every coherence protocol message, then message delivery reliability is improved, but network traffic and latency increase

Engineering Contradiction:
Improvemessage delivery reliabilityVSAvoidrecovery latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent merges the acknowledgment function with existing coherence protocol responses. When a node receives a coherence message (such as a cache access request), it sends back its standard coherence response which also serves as an acknowledgment of message receipt. This eliminates the need for separate acknowledgment messages while maintaining delivery reliability, thereby reducing network traffic and latency.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS10877836B2Method and apparatus for coherent interconnect recovery with protocol layer re-transmission
Publication Date: 2020.12.29 ARM LTD
  • US10877836B2 patent drawing
  • US10877836B2 patent drawing
  • US10877836B2 patent drawing

AI summary

A fault tolerant data processing network includes a number of nodes intercoupled through an interconnect circuit. The micro-architectures of the nodes are configured for sending and receiving messages via the interconnect circuit. In operation, a first Request Node sends a read request to a Home Node. In response, the Home Node initiates transmission of the requested data to the first Request Node. When the first Request Node detects that a fault has occurred, it sends a negative-acknowledgement message to the first Home Node. In response, the Home Node again initiates transmission of the requested data to the first Request Node. The requested data may be transmitted from a local cache of a second Request Node or transmitted by a Slave Node after being retrieved from a memory. The data may be transmitted to the first Request Node via the Home Node or directly via the interconnect.