Semiconductor Interconnect Reinforcing Layer for Thermal Stress Relief
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Solution Overview
Problem
Stress due to thermal expansion coefficient differences between components in semiconductor chips and packages leads to mechanical and electrical defects, particularly exacerbated by miniaturization and thinning trends in electronic devices, reducing reliability.
Innovation Solution
An interconnect structure featuring a conductive reinforcing layer with a plate shape extending parallel to the semiconductor substrate, electrically connected to connection bumps and covering a significant area, disperses stress by overlapping with connection bumps and providing a large footprint to alleviate stress concentrations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If semiconductor chips and packages are miniaturized and thinned, then device size is reduced, but stress concentration increases and reliability decreases
Solution Approach 1:
The patent introduces a conductive reinforcing layer that extends in the planar dimension (parallel to the substrate surface) to distribute stress laterally, compensating for the reduced vertical thickness. This dimensional approach allows stress dispersion without increasing overall device volume, resolving the contradiction between miniaturization and reliability.
Solution Approach 2:
The patent employs a composite structure combining the conductive reinforcing layer with the existing BEOL and UBM layers. This composite approach creates a multi-functional system where the conductive layer provides both electrical connectivity and mechanical stress distribution, enhancing reliability in miniaturized devices.
2Reliability
If conductive reinforcing layer is added to disperse stress, then reliability is improved, but device complexity increases
Solution Approach 1:
The conductive reinforcing layer serves dual functions: it provides electrical connectivity between connection bumps and the BEOL structure, while simultaneously acting as a mechanical reinforcement to distribute stress. This multi-functionality avoids adding separate dedicated stress-management components, thereby limiting the increase in device complexity.
Solution Approach 2:
The patent merges the electrical interconnect function with the mechanical reinforcement function into a single conductive layer structure. By combining these functions, the design avoids the complexity of separate systems and integrates stress management directly into the existing interconnect architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces damage from stress and enhances the reliability of semiconductor chips and packages by dispersing stress, improving electrical connections and mechanical integrity.
Implementation Method 1
The conductive reinforcing layer may have a plate shape with an area overlapping at least a portion of each of the plurality of connection bumps... effectively reduces damage from stress and enhances the reliability of semiconductor chips and packages by dispersing stress
Data Source
AI summary
A semiconductor chip includes a back end of line (BEOL) structure on a first surface of the semiconductor substrate and including a conductive connection structure and an interlayer insulating layer covering the conductive connection structure, a conductive reinforcing layer arranged on the BEOL structure, a cover insulating layer covering the conductive reinforcing layer, an under bump metal (UBM) layer including a plurality of pad connection portions connected to the conductive reinforcing layer through openings in the cover insulating layer, and a plurality of first connection bumps arranged on the plurality of pad connection portions of the UBM layer, electrically connected to one another through the conductive reinforcing layer, and located to overlap the conductive reinforcing layer. The conductive reinforcing layer has a plate shape and extends parallel to the first surface of the semiconductor substrate.