Interconnect Structure with Low-k Reinforcing Spacers

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The increasing density of metal lines in interconnect structures leads to greater RC delay due to parasitic resistance and capacitance, resulting in poor device performance.

Innovation Solution

The interconnect structure incorporates conductive elements formed in a patterned first dielectric layer, with multiple pairs of reinforcing spacers having a low dielectric constant, strategically placed between the conductive elements and the dielectric layer to reduce capacitance and RC delay.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If metal lines are designed to be close to each other to meet shrinkage demand, then device size is reduced, but RC delay increases due to greater parasitic resistance and capacitance

Engineering Contradiction:
Improvedevice sizeVSAvoidRC delay
Core Design Contradiction:
Volume of moving objectVSLoss of time

Solution Approach 1:

The patent applies local quality by introducing reinforcing spacers with low dielectric constant material specifically at critical locations between adjacent metal lines. This localized modification of dielectric properties reduces parasitic capacitance in high-density interconnect regions without requiring overall device size increase, thus resolving the contradiction between miniaturization and RC delay reduction.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the dielectric constant parameter of the spacer material from conventional values to lower values (comparatively low dielectric constant). This parameter change directly reduces the capacitance between adjacent metal lines, thereby reducing RC delay while maintaining the compact metal line spacing required for small device size.

Inventive Principle:
Principle #35Parameter changes

2Quantity of substance

If metal lines are densely packed to increase interconnect density, then routing capacity is improved, but capacitance between adjacent lines increases leading to greater RC delay

Engineering Contradiction:
Improveinterconnect densityVSAvoidRC delay
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The reinforcing spacers are strategically placed between adjacent metal lines in densely packed configurations. This local modification creates low-capacitance zones specifically where high interconnect density is implemented, allowing the structure to maintain high routing capacity while reducing the harmful capacitive coupling that would otherwise result from the dense packing.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The reinforcing spacers act as intermediary elements between adjacent metal lines. These spacers with low dielectric constant material serve as mediators that reduce the electric field coupling between closely spaced conductors, thereby reducing parasitic capacitance and RC delay while allowing the metal lines to remain densely packed for high interconnect density.

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The use of low dielectric constant reinforcing spacers effectively reduces capacitance between adjacent metal lines, especially in densely packed configurations, thereby minimizing RC delay and enhancing device performance.

Implementation Method 1

The reinforcing spacers have a comparatively low dielectric constant, such as not greater than about 4, and are beneficial in keeping the capacitance between adjacent ones of the metal lines along the Y direction low

Methodology Applied
Scientific EffectDielectric constant: Dielectric Permittivity

Data Source

PatentUS20250125189A1Interconnect structure with reinforcing spacer and method for manufacturing the same
Publication Date: 2025.04.17 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250125189A1 patent drawing
  • US20250125189A1 patent drawing
  • US20250125189A1 patent drawing

AI summary

A method for manufacturing an interconnect structure includes: forming a first dielectric layer; forming a mask; patterning the first dielectric layer through the mask to form a trench, an inner surface of the trench having two first portions opposite to each other along an X direction, two second portions opposite to each other along a Y direction, and a bottom portion; forming a second dielectric layer over the mask and the patterned first dielectric layer, and along an inner surface of the trench; etching the second dielectric layer by directing an etchant in a predetermined direction such that a first part of the second dielectric layer on the two first portions and the bottom portion is removed, and a second part of the second dielectric layer on the second portions of the trench remains and is formed into two reinforcing spacers; and forming a trench-filling element.