Interconnect Repair Chain Layout for Low-Delay Multiplexing
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Solution Overview
Problem
Current interconnect repair strategies in 2.5D and 3D chip designs, such as those outlined in the UCle standard, introduce significant propagation delays and require complex multiplexing schemes, inefficiently using silicon area and control signals due to the use of three-to-one multiplexers for repairing defective interconnects.
Innovation Solution
Implementing a design with multiple repair chains, each containing a single spare interconnect, and using two-to-one multiplexers to efficiently reroute signal paths around defective primary interconnects, ensuring neighboring interconnects belong to different chains to minimize propagation delay and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single repair chain with spare interconnects is used as per UCle standard, then interconnect repair capability is provided, but propagation delay increases substantially and device complexity increases due to wide multiplexers
Solution Approach 1:
The patent divides the interconnect array into multiple repair chains (at least four), where each chain contains a subset of interconnects and a single spare interconnect. This segmentation allows signals to be rerouted within smaller chains, reducing the maximum distance a signal must travel during repair operations and thereby reducing propagation delay compared to a single long repair chain.
Solution Approach 2:
The patent organizes interconnects into a two-dimensional grid structure where repair chains are formed by selecting interconnects based on their spatial coordinates (even/even, even/odd, odd/even, odd/odd positions). This dimensional organization enables efficient routing and reduces the worst-case signal path length during repair operations.
2Reliability
If three-to-one multiplexers are used for interconnect repair, then repair functionality is achieved, but silicon area increases and control signal requirements increase
Solution Approach 1:
By segmenting interconnects into multiple repair chains, each requiring only a two-to-one multiplexer instead of a single wide three-to-one multiplexer, the patent reduces the silicon area required for multiplexing circuitry. Multiple small multiplexers consume less area than one large multiplexer with the same total capacity.
Solution Approach 2:
The patent changes the multiplexer selection parameter from three inputs (requiring two select bits) to two inputs (requiring one select bit) per multiplexer instance. This parameter change reduces both the area of each multiplexer and the number of control signals required, while the overall repair functionality is maintained through the distributed chain structure.
3Reliability
If offsetting signal paths to spare interconnects is implemented, then defective interconnects are repaired, but the number of control signals increases
Solution Approach 1:
Dividing the interconnect array into multiple repair chains reduces the number of signals that need to be multiplexed at each stage. Each two-to-one multiplexer requires only one select signal, and with multiple chains operating independently, the total control signal count is reduced compared to a single large multiplexer requiring multiple select signals.
Solution Approach 2:
The patent applies repair functionality selectively to individual repair chains only when needed, rather than maintaining a complex global multiplexing structure that would require extensive control signals. Each chain can be independently activated or deactivated based on defect detection, reducing overall control complexity.
Data Source
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AI summary
An integrated circuit (1) comprising: a plurality of interconnects (2) forming at least four repair chains (A, B, C, D), each repair chain (A, B, C, D) comprising: a plurality of primary interconnects (21) for providing a signal path (3), a spare interconnect (22), and circuitry (4) configured for offsetting, within each repair chain, signal paths (3) so as to avoid the use of a defective primary interconnect (23), when present, within the repair chain (A, B, C, D), wherein one signal path (3) is offset to the spare interconnect (22), wherein the plurality of interconnects (2) is arranged so that spatially neighbouring interconnects (2) belong to different repair chains (A, B, C, D).