Semiconductor Interconnect Layer Resin Selection
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Solution Overview
Problem
The existing method of manufacturing semiconductor devices restricts the selection of resins for interconnect layers due to thermal decomposition temperature requirements, limiting the use of inexpensive resins and increasing production costs.
Innovation Solution
The method involves forming a first interconnect layer on a supporting substrate, mounting a semiconductor chip, removing the substrate, and then forming a second interconnect layer, allowing the use of a resin with a lower thermal decomposition temperature for the second interconnect layer, which is more cost-effective while maintaining fine-scale processing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a resin appropriate for fine-scale processing is employed on the interconnect layer facing the semiconductor chip, then fine-scale connection between the interconnect layer and the semiconductor chip is achieved, but the manufacturing cost increases due to the high cost of such resin
Solution Approach 1:
The patent applies different resin types to different interconnect layers based on their specific functional requirements. The first interconnect layer (facing the semiconductor chip) uses a high-performance resin appropriate for fine-scale processing, while the second interconnect layer (facing the solder balls) uses a more inexpensive resin, thereby achieving cost reduction without compromising the fine-scale connection quality where it is most critical
Solution Approach 2:
The patent inverts the conventional manufacturing sequence by first forming the first interconnect layer on the supporting substrate, mounting the semiconductor chip, removing the substrate, and then forming the second interconnect layer. This inversion removes the thermal decomposition temperature restriction that would otherwise force the use of expensive resins in both layers, allowing selective use of inexpensive resin in the second layer
2Ease of manufacture
If the interconnect layers are sequentially stacked on the supporting substrate with the solder balls side formed first, then the manufacturing process follows conventional sequence, but the resin selection is restricted by thermal decomposition temperature requirements
Solution Approach 1:
The patent inverts the conventional manufacturing sequence by first forming the first interconnect layer on the supporting substrate, mounting the semiconductor chip, removing the substrate, and then forming the second interconnect layer. This inversion removes the thermal decomposition temperature restriction that would otherwise force the use of expensive resins in both layers, allowing selective use of inexpensive resin in the second layer
Data Source
AI summary
The semiconductor device 1 includes interconnect layers 10, 20, an IC chip 30, via plugs 42, 44, a seal resin 50, and solder balls 60. The interconnect layer 10 includes a via plug 42. An end face of the via plug 42 on the side of the interconnect layer 20 is smaller in area than the opposite end face, i.e. the end face on the side of the IC chip 30. An end face of the via plug 44 on the side of the interconnect layer 10 is smaller in area than the opposite end face, i.e. the end face on the side of the solder balls 60. The thermal decomposition temperature of the insulating resin 14 constituting the interconnect layer 10 is higher than that of the insulating resin 24 constituting the interconnect layer 20.