Metallic Interconnect Resistivity Reduction via Compressive Strain
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Solution Overview
Problem
As copper interconnect structures in semiconductor fabrication are scaled down, their resistivity increases exponentially, leading to undesirable electrical performance.
Innovation Solution
Applying mechanical strain to metallic interconnect structures through a stress layer and thermal anneal process to permanently deform them into a compressive strain state, reducing electrical resistivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If copper interconnect structures are scaled down in size, then device performance and integration density are improved, but resistivity of the copper interconnect structures increases exponentially
Solution Approach 1:
The patent applies mechanical strain to the copper interconnect structure, changing its physical state and crystallographic orientation. By inducing compressive strain through a stress layer and thermal annealing process, the copper grains are reoriented to favor <100> orientation, which has lower electrical resistivity. This parameter change in the material's physical state resolves the contradiction by maintaining low resistivity even at scaled dimensions.
Solution Approach 2:
The patent utilizes differential thermal expansion between the stress layer and the copper interconnect structure. During thermal annealing, the stress layer expands more than the copper, applying compressive strain to the copper structure. This thermal expansion mechanism enables the induction of beneficial mechanical strain that reduces resistivity, resolving the scaling-related resistivity increase.
2Reliability
If mechanical strain is applied to metallic interconnect structures, then electrical resistivity is reduced, but additional process steps and structure complexity are introduced
Solution Approach 1:
The patent merges the stress layer formation with existing BEOL process steps. The stress layer is deposited as part of the interlevel dielectric structure, and the thermal annealing is combined with subsequent dielectric processing steps. This merging approach integrates the strain-induced resistivity reduction into the existing manufacturing flow without requiring separate dedicated process modules.
Solution Approach 2:
The stress layer serves as an intermediary element that transfers mechanical strain to the copper interconnect structure. Rather than directly applying complex strain mechanisms, the patent uses this intermediate stress layer that naturally generates compressive strain through thermal expansion, simplifying the overall process while achieving the desired resistivity reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively decreases the electrical resistivity of metallic interconnects by up to 10% and reduces the aspect ratio of metal lines, improving device performance and reducing parasitic capacitance.
Implementation Method 1
A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure
Implementation Method 2
apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain
Data Source
AI summary
Methods are provided for fabricating metallic interconnect structures having reduced electrical resistivity that is obtained by applying mechanical strain to the metallic interconnect structures, as well as semiconductor structures having metallic interconnect structures formed with permanent mechanical strain to provide reduced electrical resistivity. For example, a method includes forming a metallic interconnect structure in an interlevel dielectric (ILD) layer of a back-end-of-line (BEOL) structure of a semiconductor structure, and forming a stress layer in contact with the metallic interconnect structure. A thermal anneal process is performed to cause the stress layer to expand and apply compressive strain to the metallic interconnect structure and permanently deform at least a portion of the metallic interconnect structure into a stress memorized state of compressive strain.