System-Level Interconnect Ring for Programmable ICs
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Solution Overview
Problem
Modern programmable devices, such as FPGAs, face increasing costs due to advanced process technology and overhead, with traditional monolithic architectures becoming costly for applications that do not require all heterogeneous circuit blocks, leading to the development of system-in-package (SiP) devices that rely on expensive interposers or complex die stacking, limiting benefits to high-end applications.
Innovation Solution
A system-level interconnect ring for programmable integrated circuits is introduced, featuring a programmable fabric with wire tracks adjacent to its edges, integrated ring nodes between the interconnect and wire tracks, and SiP IO circuits, allowing data transmission over a smaller number of physical channels between programmable and companion ICs, reducing the need for expensive interposers and complex stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional monolithic architectures are used for programmable devices, then integration is simplified, but cost increases due to advanced process technology requirements for all circuit blocks
Solution Approach 1:
The device is divided into a programmable IC die and a companion IC die, each manufactured using different process technologies. The programmable fabric is segmented from the I/O circuits, allowing independent optimization of each component's manufacturing process and reducing overall cost.
Solution Approach 2:
The architecture transitions from a single-plane monolithic structure to a multi-die three-dimensional arrangement. The programmable IC and companion IC are stacked vertically and connected via through-silicon vias (TSVs), enabling cost-effective heterogeneous integration by utilizing the vertical dimension.
2Ease of manufacture
If advanced packaging techniques such as interposers or three-dimensional die stacking are used, then system-in-package functionality is achieved, but cost increases limiting benefits to high-end applications
Solution Approach 1:
The expensive interposer component is extracted and removed from the design. Instead, the patent uses direct die-to-die bonding with TSV connections, eliminating the interposer while maintaining signal integrity and reducing cost for standard applications.
Solution Approach 2:
The patent optimizes TSV parameters including diameter (5-10 micrometers), spacing, and metallization layers to achieve reliable signal transmission at lower costs. By carefully controlling these parameters, the design achieves adequate reliability for most applications without requiring expensive advanced packaging.
3Speed
If all circuit blocks use newer process technology, then performance is improved, but cost increases significantly
Solution Approach 1:
Different process technologies are applied to different parts of the system based on performance requirements. The programmable fabric uses newer process technology for high-speed internal operations, while the companion IC uses older, cheaper process technology for less performance-critical functions, optimizing the overall cost-performance ratio.
Data Source
AI summary
An example programmable integrated circuit (IC) includes a programmable fabric having a programmable interconnect and wire tracks adjacent to at least one edge of the programmable fabric. The programmable IC further includes at least one ring node integrated with at least one edge of the programmable fabric, the at least one ring node coupled between the programmable interconnect and the wire tracks. The programmable IC further includes a system-in-package (SiP) input/output (IO) circuit coupled to the wire tracks.