3D Interconnect Routing Layout for Reduced-Height Standard Cells

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Solution Overview

Problem

The miniaturization of integrated circuits leads to challenges in providing sufficient routing resources due to limitations in metal pitch, which restricts the number of metal tracks within a given cell height, resulting in design rule violations and inadequate power and signal routing.

Innovation Solution

The proposed solution involves advanced layout designs that optimize metal track placement and via contacts across multiple layers, allowing for reduced mask usage and increased feature density without violating design rules, using techniques like nature end processes and LSLE, to accommodate smaller cell heights and enhance routing resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If metal pitch is reduced to increase the number of metal tracks within a given cell height, then routing resources are improved, but design rule violations occur and manufacturing reliability deteriorates

Engineering Contradiction:
Improvenumber of metal tracksVSAvoiddesign rule compliance
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent introduces a third metal layer (M3) above the traditional two-layer (M1, M2) structure, transforming the routing problem from a 2D plane to a 3D space. This dimensional expansion allows additional power and signal tracks without reducing the pitch of existing layers, thereby maintaining design rule compliance while increasing routing capacity. The M3 layer provides dedicated routing resources that do not interfere with the spacing requirements of lower layers.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent segments the routing function across multiple metal layers, with M1 and M2 handling certain routing tasks and M3 handling others. This segmentation allows each layer to be optimized independently for its specific routing needs, preventing congestion and avoiding design rule violations that would occur if all routing were attempted on fewer layers with reduced pitch.

Inventive Principle:
Principle #1Segmentation

2Area of moving object

If cell height is reduced to increase feature density, then device miniaturization is achieved, but routing resources become insufficient

Engineering Contradiction:
Improvecell heightVSAvoidrouting resources
Core Design Contradiction:
Area of moving objectVSQuantity of substance

Solution Approach 1:

By adding the M3 metal layer, the patent effectively increases the vertical dimension of the routing space without increasing the cell height. This allows more routing resources to be packed into the same footprint by utilizing the third dimension (z-axis) rather than compressing features in the x-y plane, thereby maintaining feature density while increasing routing capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent nests multiple routing functions within the vertical stack of metal layers. The M1, M2, and M3 layers are nested in the vertical direction, with each layer providing additional routing resources. This nesting allows the circuit to achieve high feature density in the horizontal plane while accumulating routing resources through the vertical stack.

Inventive Principle:
Principle #7Nested doll (Nesting)

3Ease of manufacture

If mask usage is reduced to simplify manufacturing, then production costs are lowered, but design flexibility and routing options are limited

Engineering Contradiction:
Improvemask usageVSAvoidrouting options
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The M3 metal layer serves multiple functions: it provides additional power routing, signal routing, and can be used for both intra-cell and inter-cell connections. This multi-functionality allows the same structural addition (M3 layer) to address multiple routing needs simultaneously, maintaining design flexibility without requiring separate specialized structures for each function.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11854974B2Advanced node interconnect routing methodology
Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11854974B2 patent drawing
  • US11854974B2 patent drawing
  • US11854974B2 patent drawing

AI summary

One aspect of this description relates to an integrated circuit. In some aspects, the integrated circuit includes a first pattern metal layer, a second pattern metal layer disposed over the first pattern metal layer, wherein the second pattern metal layer includes a second plurality of metal tracks extending in a first direction, and a third pattern metal layer disposed between the first pattern metal layer and the second pattern metal layer, the third pattern metal layer including a first metal track segment and a second metal track segment shifted in a second direction from the first metal track segment, wherein the second plurality of metal tracks, and at least a portion of each of the first metal track segment and the second metal track segment are within a double cell height in the second direction.