Interconnect Structure Routing Yield and Mechanical Strength
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Solution Overview
Problem
Current Embedded Chip Build-Up (ECBU) technology faces challenges with increased yield loss due to additional routing layers and thinner conductor lines, which can lead to scrapped chips, and insufficient space for decoupling capacitors in thin-profile carriers, while pin grid array pins have less mechanical strength compared to ball grid array solder balls.
Innovation Solution
An interconnect structure featuring an insulative web with a logic device secured to it, a frame panel assembly with conductive layers and insulative layers, and connectors that allow for efficient communication and mounting of passive components, enabling effective routing and mechanical support.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional routing layers and thinner conductor lines are used to handle increased I/O counts, then routing capability is improved, but manufacturing precision and yield are worsened
Solution Approach 1:
The patent transitions from planar routing to three-dimensional routing by forming conductive lines and vias through the thickness of the carrier substrate. This vertical dimension allows routing signals through multiple layers without increasing lateral line density, thereby maintaining manufacturing precision while improving routing capability for high I/O counts.
Solution Approach 2:
The carrier is divided into multiple routing layers with conductive lines and vias distributed through different depths. This segmentation allows the routing function to be distributed across multiple spatial segments, reducing the complexity and precision requirements of any single layer while achieving the required total routing capacity.
2Length of stationary object
If the carrier profile is reduced to less than 1mm for thin-profile applications, then device compactness is improved, but the ability to mount decoupling capacitors is worsened
Solution Approach 1:
Decoupling capacitors are mounted within recesses or cavities formed in the carrier substrate, nesting them within the overall carrier structure. This allows the capacitors to be accommodated within the thin profile without increasing the external dimensions of the carrier, maintaining compactness while enabling component mounting.
Solution Approach 2:
Instead of mounting capacitors on the top surface (lateral dimension), the design utilizes the vertical dimension by forming recesses through the substrate and placing capacitors within these three-dimensional spaces. This allows component accommodation in the thickness direction rather than increasing the footprint.
3Ease of operation
If pin grid array pins are used instead of ball grid array solder balls, then ease of operation is improved, but mechanical strength is worsened
Solution Approach 1:
The interconnect structure uses a composite approach combining pin grid array pins with a reinforced carrier structure. The pins themselves remain simple and easy to handle, but the overall mechanical strength is enhanced through the composite construction of the carrier substrate and its integration with the logic device, achieving both ease of operation and mechanical strength.
Data Source
AI summary
An interconnect structure includes an insulative web having a first surface and a second surface; a logic device secured to the second surface of the insulative web; a frame panel assembly including a frame base having a first surface and a second surface, a first frame insulative layer disposed between the frame base first surface and the insulative web second surface, an aperture extending through the frame base and first frame insulative layer, wherein at least a portion of the logic device is disposed within the aperture, and a first frame connector disposed between a first electrically conductive layer located on the frame base first surface, and a second electrically conductive layer located on a surface of the first frame insulative layer; a device connector disposed between an I/O contact on a surface of the logic device and a third electrical conductor located on a surface of the insulative web; and an insulative layer connector that is disposed between the third electrical conductor located on a surface of the insulative web and the second electrically conductive layer located on a surface of the first frame insulative layer.