Semiconductor Interconnect Structure for Selective ALD Isolation
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Solution Overview
Problem
The semiconductor industry faces challenges in manufacturing advanced transistor structures like FinFETs due to the complexity of achieving selective deposition of isolation materials without damaging the substrate or mask layers, which affects the precision and efficiency of the fabrication process.
Innovation Solution
A bias-induced selective atomic layer deposition (ALD) process is employed, where a bias is applied to the substrate to control the distribution of charges, allowing for precise deposition of isolation materials on the substrate while minimizing deposition on mask layers, using a combination of DC and RF biases and specific precursor timing to achieve high selectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional deposition methods are used to deposit isolation materials, then the deposition process is simple, but the selectivity is poor and damage to substrate or mask layers occurs
Solution Approach 1:
The patent applies bias-induced selective atomic layer deposition (ALD) where a bias is applied to the substrate to control the distribution of charges. This changes the electrical parameter of the substrate surface to achieve selective deposition of isolation materials on specific regions while preventing deposition on mask layers, thereby improving manufacturing precision without causing damage
Solution Approach 2:
The patent replaces conventional thermal or chemical deposition mechanisms with a bias-induced electrical field mechanism. By applying DC and RF biases, the process uses electrical forces to control precursor adsorption and material deposition, enabling high selectivity and avoiding the harmful effects of high-temperature or high-energy conventional methods
2Manufacturing precision
If bias-induced selective ALD is used to improve deposition precision, then the manufacturing complexity increases
Solution Approach 1:
The patent employs periodic action by applying DC bias during precursor adsorption phases and RF bias during reaction phases. This periodic switching of bias conditions enables selective deposition control while maintaining a systematic and manageable process structure, balancing precision improvement with process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the formation of FinFET structures with precise control over the deposition of isolation materials, reducing damage and improving the manufacturing efficiency by ensuring high selectivity and uniformity, thus enhancing the overall performance and reliability of semiconductor devices.
Implementation Method 1
A bias-induced selective atomic layer deposition (ALD) process is employed, where a bias is applied to the substrate to control the distribution of charges, allowing for precise deposition of isolation materials on the substrate while minimizing deposition on mask layers
Data Source
AI summary
A device includes a conductive feature, a first dielectric layer, a via, an etch stop layer, a second dielectric layer, and a conductive line. The first dielectric layer is above the conductive feature. The via is in the first dielectric layer and above the conductive feature. The etch stop layer is above the first dielectric layer. A side surface of the etch stop layer is coterminous with a sidewall of the via. The second dielectric layer is above the etch stop layer. The conductive line is in the second dielectric layer and over the via. The conductive line is in contact with the side surface of the etch stop layer and a top surface of the etch stop layer.