Interconnect Process Variation Analysis via Sensitivity RC Netlists
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Solution Overview
Problem
Current methods for verifying integrated circuits' tolerance to process variation and parasitic resistance-capacitance (RC) elements in semiconductor manufacturing are computationally intensive and lack accuracy, particularly failing to account for inter-layer cancellation and providing overly pessimistic views of IC performance.
Innovation Solution
A method and system that generate corner RC netlists by extracting parasitic RC elements at process corners, determining sensitivity values for conductive layers, and combining them into a sensitivity RC netlist, which is then simulated using Monte Carlo methods to predict IC performance, including best and worst-case scenarios, while accounting for inter-layer cancellation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Monte Carlo simulation methods are used to verify IC tolerance to process variation, then comprehensive performance assessment is achieved, but computational complexity and time consumption increase significantly
Solution Approach 1:
The patent segments the interconnect structure into multiple conductive layers, each assigned its own process corner parameters. This allows independent analysis of each layer's contribution to overall RC variation, avoiding the need for exhaustive full-chip Monte Carlo simulations while maintaining accuracy in predicting IC performance under process variation.
Solution Approach 2:
The patent changes the simulation approach by using corner-based parameter assignment instead of traditional statistical Monte Carlo parameters. Each conductive layer is assigned specific process corner values (e.g., FF, SS, FS, SF) that represent extreme process conditions, enabling faster worst-case and best-case performance prediction without requiring numerous random sampling iterations.
2Reliability
If traditional RC extraction methods are used, then parasitic RC elements are accounted for, but inter-layer cancellation effects are missed leading to overly pessimistic performance views
Solution Approach 1:
The patent segments the RC analysis by conductive layer, allowing each layer's parasitic elements to be analyzed independently with its own process corner assignment. This segmentation enables the detection of inter-layer cancellation effects where positive and negative variations in different layers offset each other, preventing overly pessimistic worst-case predictions that treat all layers as simultaneously worst-case.
Solution Approach 2:
The patent applies local quality by assigning different process corner characteristics to different conductive layers based on their specific manufacturing variations. Instead of applying a uniform worst-case corner to all layers, each layer receives locally optimized corner parameters that reflect its actual process sensitivity, thereby capturing cancellation effects and improving overall prediction accuracy.
Data Source
AI summary
A method and a corresponding system for analyzing process variation and parasitic resistance-capacitance (RC) elements in an interconnect structure of an integrated circuit (IC) are provided. First descriptions of parasitic RC elements in an interconnect structure of an IC are generated. The first descriptions describe the parasitic RC elements respectively at a typical process corner and a peripheral process corner. Sensitivity values are generated at the peripheral process corner from the first descriptions. The sensitivity values respectively quantify how sensitive the parasitic RC elements are to process variation. The sensitivity values are combined into a second description of the parasitic RC elements that describes the parasitic RC elements as a function of a process variation parameter. Simulation is performed on the second description by repeatedly simulating the second description with different values for the process variation parameter.