Interconnect Structure With Sidewall Barrier for Low-Resistance Vias
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Solution Overview
Problem
As IC technology nodes shrink, interconnects in multilayer interconnect (MLI) features experience increased contact resistance, leading to performance, yield, and cost challenges due to delayed or prevented signal routing to and from IC devices.
Innovation Solution
The implementation of interconnect structures with low-resistance vias and metal lines, where diffusion barrier layers are selectively formed on the sidewalls of contact structures but not on the underlying interconnect features, reducing contact resistance and overall resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diffusion barrier layers are formed on all surfaces of contact structures, then diffusion protection is improved, but contact resistance increases
Solution Approach 1:
The patent applies local quality by selectively forming diffusion barrier layers only on the sidewalls of contact structures while intentionally leaving the bottom surface uncovered. This localized application provides diffusion protection where it is most needed (sidewalls) while avoiding the harmful effect of increased contact resistance at the bottom interface, thus resolving the technical contradiction between diffusion protection and contact resistance.
2Productivity
If IC feature size is reduced to increase functional density, then productivity is improved, but contact resistance increases
Solution Approach 1:
The patent enables continued scaling to higher functional densities by applying the local quality principle to contact structure design. By restricting barrier layers to sidewalls only, the invention maintains low contact resistance even as feature sizes reduce, allowing productivity improvements through increased functional density without being penalized by rising contact resistance.
Solution Approach 2:
The patent segments the diffusion barrier layer into two distinct regions: covered sidewalls and uncovered bottom surfaces. This segmentation allows independent optimization of each region's function, enabling the contact structure to achieve both diffusion protection and low contact resistance simultaneously, which is critical for maintaining performance at reduced feature sizes.
3Reliability
If barrier layers are formed conformally on contact structures, then diffusion protection is improved, but signal routing efficiency deteriorates
Solution Approach 1:
The patent applies local quality by creating non-uniform barrier layer coverage on contact structures. The sidewalls receive full barrier layer coverage for diffusion protection, while the bottom surfaces remain uncovered to maintain low contact resistance and high signal routing efficiency. This localized differentiation resolves the contradiction between diffusion protection and signal routing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance and overall resistance in interconnect structures, enhancing signal routing efficiency and addressing the challenges posed by shrinking IC technology nodes.
Implementation Method 1
forming an inhibitor film at the top surface of the conductive capping layer... depositing a barrier layer on sidewalls of the opening... the inhibitor film delays a growth of the barrier layer on the inhibitor film
Data Source
AI summary
A method of forming a semiconductor structure includes forming a conductive capping layer over a conductive feature, forming a dielectric layer over the conductive capping layer, forming an opening in the dielectric layer to expose a top surface of the conductive capping layer, forming an inhibitor film at the top surface of the conductive capping layer, depositing a barrier layer on sidewalls of the opening, removing the inhibitor film to expose the top surface of the conductive capping layer, depositing a supplementary liner on the barrier layer and the top surface of the conductive capping layer, and depositing a conductive material on the supplementary liner and filling the opening.