Conductive Interconnect Sidewall Fluorination for Lower RC Delay
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Solution Overview
Problem
The existing techniques for forming conductive interconnects in integrated circuits (ICs) using damascene processes face challenges that impact device performance, such as increased dielectric constant of interlayer dielectric (ILD) materials, moisture uptake, and metallization issues, which deteriorate resistive-capacitive (RC) delay performance.
Innovation Solution
Employing a fluorine-radical based etch process to remove the hard mask and using a barrier layer over the ILD, which converts plasma-induced damage into fluorinated silicon oxide or fluorosilicate glass (FSG) on the conductive interconnect sidewalls, thereby reducing the dielectric constant and preventing moisture uptake.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional damascene processes are used to form conductive interconnects, then the interconnect structures can be formed, but the dielectric constant of interlayer dielectric (ILD) materials increases and moisture uptake occurs, deteriorating RC delay performance
Solution Approach 1:
The patent converts plasma-induced damage, which is normally harmful, into fluorinated silicon oxide or fluorosilicate glass (FSG) on the conductive interconnect sidewalls. This fluorinated layer reduces the dielectric constant and prevents moisture uptake, transforming the harmful plasma damage into a beneficial protective structure that improves RC delay performance
Solution Approach 2:
The patent changes the chemical composition of the sidewall material by introducing fluorine through plasma treatment. This parameter change transforms the sidewall material into fluorinated silicon oxide or FSG, which has lower dielectric constant and moisture resistance properties, thereby improving the overall RC delay performance of the interconnect structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves RC delay performance by lowering the dielectric constant of the interconnect layer and minimizing moisture-related defects, enhancing overall device speed and reliability.
Implementation Method 1
conversion of the surfaces with plasma-induced damage (such as sidewalls of a conductive interconnect) into fluorinated silicon oxide or fluorosilicate glass (FSG)
Implementation Method 2
conversion of the surfaces with plasma-induced damage into fluorinated silicon oxide or fluorosilicate glass (FSG)
Data Source
AI summary
A fabrication method and associated integrated circuit (IC) structures and devices that include conductive interconnects are described. In one example, techniques for forming conductive interconnects include use of a barrier layer (e.g., in a damascene process) and hard mask removal techniques using a dry etch process with fluorine radicals, which may improve the resistive-capacitive (RC) delay performance in resulting IC structures. In one example, an IC structure includes a first layer including a device contact structure and a second layer over the first layer. In one such example, the second layer includes a conductive interconnect coupled with the device contact structure, and one or more insulator materials surrounding the conductive interconnect, where the one or more insulator materials include fluorine at sidewalls of the conductive interconnect.