Semiconductor Interconnect Sidewall Structure Against Via Stress Migration
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Solution Overview
Problem
The efficient routing of signals in complex integrated circuits is hindered by thermal expansion-induced stress migration in multi-layered interconnection structures, particularly in high-density semiconductor devices.
Innovation Solution
Incorporation of a rigid dielectric sidewall between metal vias and low-k inter-level dielectric layers to mitigate stress migration, using materials with higher rigidity, thermal expansion coefficients, and dielectric constants to protect the low-k dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a multi-layered interconnection structure is used for efficient signal routing, then signal routing efficiency is improved, but thermal expansion-induced stress migration occurs in high-density devices
Solution Approach 1:
A rigid dielectric sidewall layer is introduced as an intermediary between the metal via and the low-k inter-level dielectric layer. This sidewall layer acts as a mediator that prevents direct stress transfer from the thermally expanding metal via to the low-k dielectric, thereby eliminating stress migration while preserving the multi-layered interconnection structure's signal routing efficiency.
Solution Approach 2:
The interconnection structure employs a composite material approach by combining metal vias with a rigid dielectric sidewall layer and low-k inter-level dielectric layer. This composite structure leverages the high rigidity and appropriate thermal expansion coefficient of the sidewall material to protect the low-k dielectric from stress migration, maintaining both structural integrity and electrical performance.
2Reliability
If low-k inter-level dielectric layer is used to reduce capacitance, then electrical performance is improved, but stress migration occurs due to thermal expansion mismatch
Solution Approach 1:
The rigid dielectric sidewall serves as a protective intermediary that isolates the low-k inter-level dielectric layer from the thermal expansion stresses of the metal via. This allows the low-k dielectric to maintain its electrical performance benefits without suffering from stress migration, as the sidewall absorbs and redirects the thermal stress away from the low-k material.
Solution Approach 2:
The invention changes the physical parameters of the interconnection structure by introducing a material with specific rigidity and thermal expansion properties. The sidewall layer's higher rigidity and carefully selected thermal expansion coefficient create a gradient that protects the low-k dielectric, allowing it to maintain low capacitance without stress migration issues.
3Device complexity
If metal via is directly surrounded by low-k dielectric layer, then device complexity is reduced, but stress migration damages the dielectric layer
Solution Approach 1:
The rigid dielectric sidewall is introduced as a thin intermediary layer between the metal via and the low-k dielectric layer. While this adds one additional layer, the sidewall is formed as a conformal coating that integrates seamlessly into the existing interconnection process flow, minimizing the increase in device complexity while providing critical protection against stress migration.
Solution Approach 2:
Rather than changing the entire interconnection structure, the invention applies a localized solution by forming a dielectric sidewall only in the specific region where stress migration occurs (at the via-dielectric interface). This localized approach protects the low-k dielectric layer integrity without significantly increasing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents stress migration, enhancing the structural integrity and electrical performance of semiconductor interconnections by maintaining the low-k dielectric layer's integrity under thermal stress.
Implementation Method 1
a diffusion barrier layer disposed around the upper metal via, and disposed between the upper inter-level dielectric layer and the upper metal via
Implementation Method 2
The efficient routing of signals in complex integrated circuits is hindered by thermal expansion-induced stress migration in multi-layered interconnection structures
Implementation Method 3
thermal expansion-induced stress migration in multi-layered interconnection structures
Data Source
AI summary
A semiconductor interconnection structure includes a lower inter-level dielectric layer located above a substrate, a lower metal via located in the lower inter-level dielectric layer, a first horizontal dielectric layer located over the lower inter-level dielectric layer and the lower metal via, an upper inter-level dielectric layer located over the first horizontal dielectric layer and having a dielectric constant smaller than that of the first horizontal dielectric layer, an upper metal via located in the upper inter-level dielectric layer and the first horizontal dielectric layer, and electrically connected to the lower metal via, a diffusion barrier layer located around the upper metal via, and located between the upper inter-level dielectric layer and the upper metal via; and a dielectric sidewall located the diffusion barrier layer and the upper inter-level dielectric layer.