Interconnect Spreading for DRC Clean Routing
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Solution Overview
Problem
Traditional electronic design methods for integrated circuits face challenges in reducing critical areas and improving yield and performance, particularly due to fixed interconnect boundaries in switch-box approaches that necessitate excessive jogs and violate design rules.
Innovation Solution
The method involves identifying interconnects and associated design rules to perform a spreading process on one-dimensional design data, allowing interconnects to be moved to adjacent tracks, and iteratively applying Boolean operations to modify interconnects while ensuring compliance with design rules, thereby reducing cross-coupling and improving timing performance and yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If traditional switch-box routing approach is used, then routing structure is simple and easy to implement, but interconnect boundaries are fixed which necessitates excessive jogs and violates design rules
Solution Approach 1:
The patent applies dynamics by transforming the fixed interconnect boundaries of traditional switch-box routing into dynamic, movable boundaries. The interconnects are allowed to spread and move to adjacent tracks during the routing process, enabling the design to adapt to design rules while maintaining routing simplicity. This is achieved through iterative spreading operations that adjust interconnect positions based on design rule violations.
Solution Approach 2:
The patent changes the parameter of interconnect position from fixed to variable. By allowing interconnects to change their track positions through spreading operations, the system can resolve design rule violations without requiring complex routing structures. The spreading distance and direction are adjusted iteratively to achieve compliance while maintaining ease of implementation.
2Ease of manufacture
If traditional switch-box routing approach is used, then routing implementation is straightforward, but excessive jogs are created which increase critical areas and reduce yield
Solution Approach 1:
The patent uses dynamics to eliminate excessive jogs by allowing interconnects to dynamically adjust their positions. Instead of being constrained to fixed switch-box boundaries that force sharp angular changes (jogs), interconnects can spread continuously to adjacent tracks, creating smoother routing paths that reduce critical areas and improve yield.
Solution Approach 2:
The patent applies dimensionality change by allowing interconnects to move not only along their primary routing direction but also to adjacent tracks (adding a lateral dimension). This extra degree of freedom enables the routing to avoid excessive jogs by distributing the interconnect path across multiple tracks, thereby reducing critical areas and improving manufacturing yield.
3Reliability
If iterative analyses and repetitive DFM techniques are applied, then yield and performance may be improved, but runtime increases significantly
Solution Approach 1:
The patent applies preliminary action by performing spreading operations during the routing phase itself, rather than requiring separate iterative post-routing optimization steps. By proactively adjusting interconnect positions to satisfy design rules and optimize performance during the initial routing process, the system achieves high yield without the need for time-consuming repetitive analyses and corrections later in the design flow.
4Device complexity
If interconnects are constrained to fixed boundaries, then routing structure is simplified, but timing performance deteriorates due to excessive jogs
Solution Approach 1:
The patent uses dynamics to resolve the timing performance issue by allowing interconnects to dynamically position themselves optimally. Instead of being forced into fixed boundaries that create excessive jogs and increase signal propagation delay, interconnects can spread to adjacent tracks to create more direct, shorter paths, thereby improving timing performance while maintaining relatively simple routing structure.
Data Source
AI summary
One aspect identifies an interconnect and associated design rule(s) and moves a portion of the interconnect to an adjacent track by using a spreading process on a one-dimensional design data based on the design rule(s) to determine whether the interconnect including the moved portion provides a DRC clean implementation. This aspect examines an interconnect in its entirety without being confined within a prescribed boundary of a fixed region in the layout. The one-dimensional design data provides expedient runtime and may be converted back into two-dimensional form for the layout. Another aspect iterates through multiple spreading distances to route or modify interconnects in a layout by performing multiple Boolean operations on the interconnect and adjacent shape(s) to determine the final form of the newly created or modified interconnect complying with various design rules.