Programmable Interconnect SRAM Locking Against Single Event Upsets
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Solution Overview
Problem
Programmable integrated circuits, such as FPGAs, are susceptible to single event upsets (SEUs) due to radiation, which can cause incorrect bit changes in SRAM cells, leading to functional failures, especially as device sizes decrease and operating voltages are reduced, increasing manufacturing costs.
Innovation Solution
The implementation of a static memory cell with a lock-state circuit that includes selectably switched signal paths and logic gates to maintain the state of memory cells, preventing changes during runtime and ensuring correct functionality by coupling outputs to a reference voltage when configuration is complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If device sizes are reduced to lower manufacturing costs, then manufacturing cost decreases, but susceptibility to single event upsets increases
Solution Approach 1:
The lock-state circuit is activated before normal operation to prevent single event upsets from altering configuration memory cell states. By preemptively locking the memory cells against radiation-induced changes, the circuit counteracts the increased susceptibility caused by smaller device sizes, thus maintaining reliability while allowing cost-effective miniaturization
Solution Approach 2:
Redundant locking circuitry is introduced in advance to protect configuration memory cells from single event upsets. This cushioning mechanism absorbs the impact of radiation effects that would otherwise cause functional failures, enabling the use of smaller, more cost-effective devices without sacrificing reliability
2Use of energy by moving object
If operating voltages are reduced to lower power consumption, then power consumption decreases, but susceptibility to single event upsets increases
Solution Approach 1:
The lock-state circuit is engaged before operation to preemptively prevent single event upsets from affecting configuration memory cells. This allows the system to operate at reduced voltages for lower power consumption while the locking mechanism counteracts the increased vulnerability to radiation effects that accompanies lower operating voltages
3Reliability
If lock-state circuit is activated to prevent SEUs, then reliability improves, but device complexity increases
Solution Approach 1:
The protection mechanism is segmented and integrated at the individual memory cell level rather than requiring a system-wide complex protection circuit. Each configuration memory cell receives dedicated lock-state protection, distributing the complexity across multiple simple identical units rather than one complex centralized system
Solution Approach 2:
The lock-state circuit provides more protection than strictly necessary by locking all configuration memory cells regardless of their criticality. This excessive action simplifies the design by using a uniform protection approach for all cells rather than implementing complex selective protection logic that would differentiate between critical and non-critical cells
Data Source
AI summary
In one embodiment of the present invention, a programmable interconnect circuit is provided. The programmable interconnect circuit includes first and second static random access memory cells, each having a first output and a second output. The second output is an inversion of the first output. First and second pass gates are each coupled to one of the first and second outputs of the respective first and second memory cells. First and second lock-state circuits are coupled to the respective first and second memory cells. In response to a configuration status signal and the first output of one of the memory cells being asserted to a low voltage, the respective lock-state circuit is configured to maintain the one of the outputs of the respective memory cell at the low voltage.