High-Density Interconnect Stack Without TSV Stress and Buckling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current high density interconnect structures face challenges such as tensile stress, via buckling, and complex routing due to via fabrication, leading to increased costs and yield loss, particularly in the use of through-silicon vias (TSVs) and silicon interposers, which complicate the manufacturing process and result in less dense routing and larger product sizes.
Innovation Solution
The implementation of a high density interconnect structure using a dual damascene stack with alternating metallization and dielectric layers, including high k, medium k, and low k dielectric materials, which reduces mechanical stress and improves electrical performance by optimizing dielectric constants and layer thicknesses, allowing for higher routing density without the need for TSVs or silicon interposers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If through-silicon vias (TSVs) are used to provide electrical interconnect, then interconnect length is reduced and performance is improved, but tensile stress and compressive hoop stresses are induced leading to via buckling and die cracking
Solution Approach 1:
The patent changes the physical state and dimensions of vias by transitioning from through-silicon vias to embedded vias that terminate within the substrate. This parameter change eliminates the through-hole structure that causes hoop stresses, thereby preventing via buckling and die cracking while maintaining electrical interconnect functionality
Solution Approach 2:
The patent extracts the problematic through-hole structure from the design by using embedded vias that do not penetrate completely through the substrate. This removal of the through-hole configuration eliminates the source of tensile and compressive stresses that lead to via buckling and die cracking
2Quantity of substance
If TSVs are used for electrical interconnect, then routing density can be increased, but manufacturing complexity and yield loss increase
Solution Approach 1:
The patent employs standard embedded via fabrication processes that are already established in semiconductor manufacturing, replacing the complex TSV process. This uses conventional, well-understood manufacturing techniques to achieve high routing density without the added complexity and yield loss associated with TSV fabrication
3Ease of operation
If silicon interposers with TSVs are used, then I/O access is improved, but product size increases
Solution Approach 1:
The patent transitions from vertical through-silicon interconnects to a more distributed embedded via architecture within the substrate plane. This dimensional reorganization allows I/O access to be achieved through lateral routing combined with embedded vias, reducing the need for large silicon interposers and thereby decreasing overall product size
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances electrical performance by reducing capacitance per unit length, inter-symbol interference, and power consumption while maintaining high routing density, thereby reducing product size and cost, and improving manufacturing yield.
Implementation Method 1
dual damascene stack with alternating metallization and dielectric layers, including high k, medium k, and low k dielectric materials, which reduces mechanical stress
Implementation Method 2
including high k, medium k, and low k dielectric materials, which reduces mechanical stress and improves electrical performance by optimizing dielectric constants
Data Source
Figure 1
Figure 2
Figure 3
AI summary
Discussed generally herein are methods and devices including or providing a high density interconnect structure. A high density interconnect structure can include a stack of alternating dielectric layers and metallization layers comprising at least three metallization layers including conductive material with low k dielectric material between the conductive material, and at least two dielectric layers including first medium k dielectric material with one or more first vias extending therethrough, the at least two dielectric layers situated between two metallization layers of the at least three metallization layers, a second medium k dielectric material directly on a top surface of the stack, a second via extending through the second medium k dielectric material, the second via electrically connected to conductive material in a metallization layer of the three or more metallization layers, and a pad over the second medium k dielectric material and electrically connected to the second via.